FET100 "Advanced Electrostatic Discharge Technology Issues"

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IEEE Electron Devices Society (EDS)
Seventh Mexico Technical Meeting 2025 (MTM_7-2025)
Mexico Chapter and Cinvestav Zacatenco Student Branch Chapter
Center for Research and Advanced Studies of the National Polytechnic Institute, Mexico

 

 


The IEEE Electron Devices Society (EDS) Cinvestav Zacatenco Student Chapter, in collaboration with the Department of Electrical Engineering – Section of Solid-State Electronics (SEES), Cinvestav, is pleased to host this IEEE EDS Distinguished Lecture as part of the global FET100 campaign, celebrating 100 years of the Field Effect Transistor.

The event is open to students, researchers, and professionals interested in electronics, semiconductors, and solid-state devices.



  Date and Time

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  • Avenida Instituto Politécnico Nacional 2508
  • Colonia San Pedro Zacatenco, Miguel Bernard La Escalera
  • Mexico City, Mexico
  • Mexico 07360
  • Building: Cinvestav, Department of Electrical Engineering
  • Room Number: Auditorium Ing. Jorge Suárez Díaz
  • Click here for Map

  • Contact Event Hosts
  • Anisleidy Broche Forte, Eng. ; anisleidy.broche.f@cinvestav.mx;

    Maricela Meneses Meneses, PhD. ; maricela.meneses.m@cinvestav.mx;

     

     

  • Co-sponsored by Department of Electrical Engineering – Section of Solid-State Electronics (SEES), Cinvestav, Mexico; CCE 2025 – International Conference on Electrical Engineering, Computing Science and Automatic Control
  • Starts 19 September 2025 11:22 PM UTC
  • Ends 23 October 2025 03:30 AM UTC
  • No Admission Charge


  Speakers

Charvaka, PhD of Texas Instruments Fellow Emeritus

Topic:

“Advanced Electrostatic Discharge Technology Issues”

"Advanced Electrostatic Discharge Technology Issues"

presented by

Charvaka Duvvury, PhD

Distinguished Lecturer, Texas Instruments Fellow Emeritus

Abstract:

Electrostatic Discharge (ESD) has been a constant reliability concern for IC technologies for several decades, and it is heading to be a roadblock to newer applications for electronic devices. The seminar will begin with the fundamentals of the ESD threat and how this led to the development of protection designs at the IC level and at the system level. These IC-level protection circuits face different challenges for Digital, Analog, and RF circuits. While on-chip protection design is essential for the IC package devices, external ESD events must be addressed at the system interfaces, such as USB and HDMI ports. The seminar will present a review of these different design strategies and address the problems posed by advanced technologies while meeting the ultra-IO high-speed performance requirements. The talk will conclude with a survey of the upcoming challenges from emerging technologies such as GaN and CNT, as well as IoT applications. Some of the critical issues of electrical overstress (EOS) during automotive applications will also be reviewed. The talk will end with the future of AI applications for ESD design and data analysis. Some opportunities for university research into the next decade will also be highlighted. 

 

Biography:

 

Charvaka Duvvury, PhD

Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group at TI. He received his PhD in engineering science from the University of Toledo and afterwards worked as a post-doctoral fellow in Physics at the University of Alberta. His experience at Texas Instruments spanned 35 years in semiconductor device physics with pioneering development work in ESD design. He has also mentored PhD students at several leading US universities on their investigations in ESD research and received the Outstanding Industry Mentor Award twice from the SRC. Charvaka has published over 150 papers in technical journals and conferences and holds more than 75 patents. He co-authored and contributed to 5 books on the subject. He is a recipient of the IEEE Electron Devices Society’s Education Award and Outstanding Contributions Award from the EOS/ESD Symposium. Charvaka served on the Board of Directors of the ESD Association (ESDA) for 25 years, promoting ESD education and research at academic institutes. He has been the co-founder and co-chair of the Industry Council on ESD since 2006. In 2015, he became a co-founder of iT2 Technologies, which utilizes a software engine and machine learning for rapid ESD data analysis. Charvaka is also a Fellow of the IEEE.

Email:

Address:Texas, United States





Agenda

MTM_7-2025 – Schedule

Time     Activity Speaker
10:20 – 10:25 Opening and Welcome Remarks Host and Facilitator
10:25 – 11:20 Advanced Electrostatic Discharge (ESD) Technology Issues Charvaka Duvvury, PhD. – Distinguished Lecturer



MTM_07-2025 is an IEEE-EDS-sponsored technical meeting. Co-sponsored by the Department of Electrical Engineering – Section of Solid-State Electronics at the Center for Research and Advanced Studies of the National Polytechnic Institute.