IEEE EPS- Seminar on Photonic Integrated Circuit (PIC) Integration and Testing
We are pleased to invite you to our upcoming Seminar on Photonic Integrated Circuit (PIC) Integration and Testing, featuring four expert talks that highlight the latest advances, methodologies, and applications in the field.
Program Overview:
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Wafer Level PIC Testing
Dr. Pascal Stark, Staff Engineer at Lumiphase AG -
Packaging Photonic Chips for Diagnostic Tools
Dr. Mark Fretz, Packaging Expert at CSEM SA -
PICs-based Comb Lasers: From Prototypes to Volume Production
Dr. Johana Bernasconi, Lead Engineer at Enlightra -
Swiss PIC: Switzerland’s New Centre for PIC Packaging
Dr. Peter Moselund, CTO/CFO of Swiss PIC
This seminar will provide valuable insights into photonic integration and testing, covering everything from wafer-level testing and packaging to advanced laser technologies and Switzerland’s national PIC packaging initiatives. It is an excellent opportunity to exchange knowledge and network with fellow professionals in the field.
Date and Time
Location
Hosts
Registration
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Add Event to Calendar
- ETH Zürich
- Zürich, Switzerland
- Switzerland 8092
- Building: To be anounced
- Room Number: To be anounced
- Click here for Map
- Starts 18 September 2025 10:00 PM UTC
- Ends 24 October 2025 10:00 PM UTC
- No Admission Charge
Agenda
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15:00 – 15:10 | Welcome & Opening Remarks
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15:10 – 15:40 | Wafer Level PIC Testing
Dr. Pascal Stark, Staff Engineer at Lumiphase AG -
15:40 – 16:10 | Packaging Photonic Chips for Diagnostic Tools
Dr. Mark Fretz, PhD, Packaging Expert at CSEM SA -
16:10 – 16:40 | PICs-based Comb Lasers: From Prototypes to Volume Production
Dr. Johana Bernasconi, Lead Engineer at Enlightra -
16:40 – 17:10 | Swiss PIC: Switzerland’s New Centre for PIC Packaging
Dr. Peter Moselund, CTO/CFO at Swiss PIC -
17:10 – 18:30 | Networking & Apéro