IEEE DL Expert Talk - High Performance CMOS Devices by Engineering High-k Gate Stack on SiGe/Ge Channel
The IEEE joint Chapter of EDS and SSCS and IEEE Gujarat Section are organizing IEEE Distinguished Lecturer Expert Talk. The details of the Talk are as follows:
Topic - High Performance CMOS Devices by Engineering High-k Gate Stack on SiGe/Ge Channel.
Speaker: Prof. Kuei-Shu Chang Liao from National Tsing Hua University, Taiwan
Date and Day: 21st November 2025, Friday
Time: 4 to 5 pm (IST)
Venue: Dhirubhai Ambani University (DAU), formerly DA-IICT, Gandhinagar, Gujarat, India
The session will highlight challenges in devices sub 3nm technology node. Henceforth, its mitigation using High-K Gate Stack on SiGe/Ge Channel. The session can be fruitful for comprehending future nano-scale devices, associated challenges and performance improvement methodologies.
Please refer the attached corresponding flyer for more information.
The registration is free, however mandatory. This can be done at
https://forms.gle/gxQwxbK6qvkWFMcP9
For any query, please contact @ Dr. Yash Agrawal, yash_agrawal@dau.ac.in, +91-9882114669
Thanks and Regards
IEEE EDS, SSCS, Gujarat Section, India
Date and Time
Location
Hosts
Registration
-
Add Event to Calendar
Speakers
Prof Liao
High Performance CMOS Devices by Engineering High-k Gate Stack on SiGe/Ge Channel
Process development of gate stack and channel in CMOS device is the key challenge beyond sub-3 nm technology node. The application of high-k dielectric or alloy in gate stack demonstrates both low EOT and gate leakage current. However, carrier mobility degradation caused by high-k gate dielectric is an issue for high performance device. SiGe/Ge channel is promising to replace Si due to its higher carrier mobility and compatible material properties. Since the properties of high-k/Ge interfaces are usually poor, the interface quality is a critical issue to realize high performance Ge MOSFETs. In this talk, engineering interface and buffer layers for SiGe/Ge MOSFETs, HfO2/ZrO2/HfO2 gate stack for FinFET, Ge n/p-FinFETs with super-critical fluid treatments, and n/p-FinFETs with SiGe/Si super-lattice channel will be presented. Low EOT, low gate leakage current, and high mobility in SiGe/Ge FinFET/GAAFET can be simultaneously achieved.
Biography:
Kuei-Shu Chang-Liao received the B.S. and M.S. degrees in Telecommunication and Electronics from National Chiao Tung University in 1984 and 1989, respectively, and the Ph.D. degree in Electrical Engineering from National Taiwan University in 1992. In 1992, Dr. Chang-Liao joined the faculty at the National Tsing Hua University where he has been a Professor of Department of Engineering and System Science since 1999. In 2000, he was a visiting research fellow at the Department of Electrical Engineering of Yale University, where he was involved in Flash memory and charge pumping measurement. During 2007-2010, he served as the Associate Chairman of Department of Engineering and System Science, and served as the Chairman during 2022-2024. His current research interests include high-k/metal gate stack processes in FinFET/GAAFET, Ge or SiGe MOS devices, charge-trapping flash memory devices, trap analysis in MOS device by charge pumping measurement, and radiation effects on semiconductor devices. Dr. Chang-Liao is a Distinguished Lecturer of IEEE EDS, senior member of IEEE, and member of the Electrochemical Society. He served as the Editor of IEEE Electron Device Letters during 2012-15. He received the excellent Industry-Academic Research Award from Ministry of Education in 2003. He has published over 400 papers in prestigious journals and conferences. He has chaired and served as committee members in several international conferences.
Email:
Address:Department of Engineering and System Science, National Tsing Hua University, TAIWAN, Taiwan
Media
| High Performance CMOS Devices by Engineering High-k Gate Stack on SiGe/Ge Channel | 1.11 MiB | |
| Event_Pic | 509.93 KiB |