Semiconductor Reliability Topics for Advanced CMOS Technologies

#CMOS #Reliability #High-K
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As we continue the relentless drive towards smaller semiconductor device feature sizes and higher levels of integration at the chip level, it has become increasingly evident that a judicious review and a very complete understanding of the reliability mechanisms that contribute to the degradation of each of the technology elements will be crucial for the successful development of the most advanced leading edge technologies. The increased device count and process complexity, coupled with ever decreasing margins in voltage, geometry and the incorporation of new material systems like high and low k dielectrics, stress/strain layers, and other limiting factors will be discussed from the reliability perspective. A closer look will be given to Hot Carriers, Bias Temperature Instabilities and statistical variations (process and geometric). This talk will also present a practical approach to the qualification methodology for advanced technologies while providing a review of the practical implications of the above mentioned reliability mechanisms. The impact of reliability induced parameter degradation and the mitigation of these effects will be analyzed for switching circuits and put in the required perspective for the successful technology transfer to a manufacturing environment.

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  • 161 Warren Street
  • Newark, New Jersey
  • United States 07102
  • Building: ECE Building, Room 202, NJIT
  • Click here for Map

  • Contact Event Host
  • Dr. Durga Misra (973) 596-5739 (dmisra “AT” njit.edu) or Dr. Edip Niver (973) 596-3542 (NJIT)
  • Co-sponsored by NJIT
  • Starts 11 February 2011 04:00 PM UTC
  • Ends 06 April 2011 09:00 PM UTC
  • No Admission Charge


  Speakers

Fernando Guarín Fernando Guarín

Topic:

Semiconductor Reliability Topics for Advanced CMOS Technologies

As we continue the relentless drive towards smaller semiconductor device feature sizes and higher levels of integration at the chip level, it has become increasingly evident that a judicious review and a very complete understanding of the reliability mechanisms that contribute to the degradation of each of the technology elements will be crucial for the successful development of the most advanced leading edge technologies. The increased device count and process complexity, coupled with ever decreasing margins in voltage, geometry and the incorporation of new material systems like high and low k dielectrics, stress/strain layers, and other limiting factors will be discussed from the reliability perspective. A closer look will be given to Hot Carriers, Bias Temperature Instabilities and statistical variations (process and geometric). This talk will also present a practical approach to the qualification methodology for advanced technologies while providing a review of the practical implications of the above mentioned reliability mechanisms. The impact of reliability induced parameter degradation and the mitigation of these effects will be analyzed for switching circuits and put in the required perspective for the successful technology transfer to a manufacturing environment.

Biography: Dr. Guarin is a Senior Engineer/Scientist at the IBM Microelectronics Semiconductor Research Development Center SRDC in East Fishkill N.Y. He received his BSEE from the “Pontificia Universidad Javeriana”, in Bogotá, Colombia, the M.S.E.E. degree from the University of Arizona, and the Ph.D. in Electrical Engineering form Columbia University. His doctoral research studied the Molecular Beam Epitaxial growth of Silicon based alloys for device applications. He has been actively working in microelectronic reliability for 30 years. From 1980 until 1988 he was a member of the Military and Aerospace Operations division of National Semiconductor Corporation where he held positions both in engineering and management. In 1988 he joined the IBM microelectronics division where he has worked in the reliability physics and modeling of Advanced Bipolar, CMOS and Silicon Germanium BiCMOS technologies. He has been the team leader for the qualification of several of IBM’s leading edge CMOS and SiGe technologies. He holds 9 patents, one trade secret, has published more than 65 papers and delivered 4 tutorials at the IEEE’s International Reliability Physics Symposium. Dr. Guarín is an IEEE Fellow, Distinguished Lecturer for the IEEE Electron Device Society a member of the IEEE EDS Ad.Com and Education Committees. He is the past Chair for the Electron Devices Society in the IEEE’s MHV Chapter, and past president of the Society of Hispanic Professional Engineers SHPE for the Mid Hudson valley Region.

Email:

Address:Semiconductor Research and development Center IBM Microelectronics B-330C-1R23, Zip/20A 2070 , Route 52, Hopewell Junction, New York, United States, 12533

Fernando Guarín of IBM

Topic:

Semiconductor Reliability Topics for Advanced CMOS Technologies

Biography:

Email:

Address:Hopewell Junction, New York, United States






Agenda

4:30 PM: Networking

4:45 PM: Pizza & Soda

5:00 PM: Talk