Pieter

In this review presentation, we will have a look at ADC efficiency trends over the years as function of ADC architecture, resolution, and sampling rate. After that, state-of-the-art design examples from literature are reviewed, and the key techniques to achieve high efficiency are highlighted. This includes techniques at circuit, system, layout and algorithmic levels. ADC architectures such as Pipelined, Sigma-Delta, SAR, Noise-Shaping SAR, and others are all briefly covered. The presentation concludes with a reflection on the differences and similarities of the highlighted efficiency features.

Biography:

Pieter Harpe (SM'15) received the MSc and PhD degrees from the Eindhoven University of Technology, The Netherlands, in 2004 and 2010, respectively. In 2008, he started as researcher at Holst Centre / imec, The Netherlands, where he worked on ultra low-power wireless transceivers, with a focus on ADC research and design. In April 2011, he joined Eindhoven University of Technology where he is currently an Associate Professor and lead of the Resource Efficient Electronics Lab. His main activities are on low-power analog and mixed-signal circuits, for instance for biomedical applications, internet of things, and edge AI. Dr. Harpe is TPC member for ISSCC and A-SSCC, Associate Editor for TCAS-I, SSCS AdCom Member-at-Large and SSCS Distinguished Lecturer. He previously served as TPC member for ISSCC, TPC member and track chair for ESSCIRC/ESSERC and co-organizer for AACD, was an IEEE SSCS Distinguished Lecturer in 2016/2017, and is recipient of the ISSCC 2015 Distinguished Technical Paper Award.

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Address:Netherlands