IEA: A Test Data Analytic Platform via Natural-Language-to-Code

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IEA: A Test Data Analytic Platform via Natural-Language-to-Code

The Intelligent Engineering Assistant (IEA) was first introduced in 2018 as an early attempt to apply AI-driven automation to post-silicon test engineering. Since then, the rapid evolution of Large Language Models (LLMs) has profoundly shaped IEA’s trajectory. With each new generation of LLMs offering stronger reasoning and programming capabilities, IEA has undergone fundamental architectural redesigns to take advantage of these advances. In 2025, IEA is re-architected once again—this time to leverage the emerging power of high-quality code generation as a central mechanism for engineering productivity.  Over the past five months, we deployed the latest IEA in an industrial environment. This deployment has transformed IEA from a research concept into a production-grade platform that measurably improves productivity and promotes broad cross-team collaboration. The 2025 IEA introduces a strengthened grounding strategy that aligns natural-language prompts with real engineering context. The system performs dynamic grounding using data tables, enabling IEA to interpret intent with direct access to datasets. Building on these capabilities, IEA automatically generates analytic Python code tailored to user prompts, allowing engineers to rapidly validate hypotheses and iterate on workflows.  Drawing from our deployment experience, we discuss observed shifts in engineering practice, the architectural insights gained throughout IEA’s evolution, and lessons learned from integrating LLM-based automation into complex industrial environments.


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  • Starts 18 February 2026 05:00 AM UTC
  • Ends 17 March 2026 04:00 PM UTC
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Professor Li-C. Wang

Topic:

IEA: A Test Data Analytic Platform via Natural-Language-to-Code

Biography:

Li-C. Wang is a Professor in the Electrical and Computer Engineering Department at the University of California, Santa Barbara. He received his Ph.D. from the University of Texas at Austin and previously worked at Motorola’s PowerPC Design Center. Since 2003, his research has focused on applying machine learning and AI to semiconductor design and test flows, resulting in over 100 papers and 22 supervised Ph.D. theses.  He has received 12 Best Paper Awards—including recent awards at the International Test Conference (ITC) in 2024–2022 and 2020—and the 2010 SRC Technical Excellence Award for his work in data mining for test and validation. He is also the recipient of the IEEE TTTC Bob Madge Innovation Award (2017). An IEEE Fellow, he served as Program Chair (2016) and General Chair (2017, 2018, 2023) of ITC.

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