Chip Craft-2026: Hands on VLSI Design and verification Boot Camp

#Chip #Craft #IEEE #young #professional #Sponserd #event #foundation #VLSI #hands #on #workshop
Share

 

Chip Craft-2026: Hands-on VLSI Design and Verification Bootcamp

Organized by the IEEE Student Branch MRIT and ERA association, Sponsered by IEEE Young Professionals and IEEE foundation in collaboration with Cranes Varsity 

 

Chip Craft-2026 is an intensive hands-on training bootcamp on VLSI Design and Verification aimed at equipping students with practical industry-relevant skills. The program focuses on fundamental and advanced concepts of digital design, verification methodologies, and real-time implementation using modern EDA tools.

The bootcamp includes expert lectures, practical lab sessions, and interactive discussions led by experienced industry professionals. Participants will gain exposure to VLSI design flow, RTL design, verification techniques, and tool-based implementation, helping them bridge the gap between academic learning and industry requirements.

This initiative by IEEE Young Professionals and the IEEE Student Branch aims to prepare students for careers in the semiconductor and VLSI industry by providing experiential learning and mentorship.


  Date and Time

  Location

  Hosts

  Registration


  • Add_To_Calendar_icon Add Event to Calendar
  • Mysururoyal Royal Institute of Technology
  • Department of ECE
  • Mandya, Karnataka
  • India 571606
  • Building: Rashtra kavi kuvempu seminar hall
  • Contact Event Host

  • Ms. Ramyashree A.N

    Branch Counscelor, IEEE student Branch MRIT

    Email:ramyanarayan.an26@gmail.com,  Contact No: 9980457092

     

    Ms. Jyothi M.P

    Event coordinator, Associate Professor, Dept. of ECE, MRIT

    Email:jyothimp@mysururoyal.org, Contact No: 9916927391

  • Co-sponsored by IEEE Young professional and IEEE Foundation
  • Survey: Fill out the survey
  • Starts 01 March 2026 06:30 PM UTC
  • Ends 08 March 2026 06:30 PM UTC
  • No Admission Charge

  Speakers

KANCHANA H of Cranes Varsity

Topic:

Hands on VLSI Design and verification

Ms. Kanchana H is a Subject Matter Expert and Corporate Trainer in Embedded Systems and VLSI Design with over 14 years of experience in technical training and industry-oriented education. She holds an M.Tech degree and is currently pursuing her Ph.D. Her expertise includes ARM Processors, Embedded C, Python, ESP32 with MicroPython, Verilog HDL, SystemVerilog, Static Timing Analysis, and FPGA Design.

She has trained over 10,000 students and professionals, contributing more than 20,000 man-hours of training across academic institutions and corporate organizations. Her work focuses on bridging the gap between academic learning and industry requirements, helping students build practical skills in embedded systems and semiconductor technologies.

 
 

Biography:

 

Ms. Kanchana H holds an M.Tech degree and is currently pursuing her Ph.D. She is a Subject Matter Expert and Corporate Trainer in Embedded Systems and VLSI Design, with over 14 years of experience in both corporate and academic training.

She has extensive expertise in delivering technical training on ARM Processors, Embedded C, Python, ESP32 with MicroPython, Verilog HDL, SystemVerilog, Static Timing Analysis, and FPGA Design. Over the course of her career, she has trained more than 10,000 participants, including students, fresh graduates, working professionals, and corporate clients, contributing over 20,000 man-hours of training.

Her technical expertise also includes FPGA platforms such as Zynq SoC, Spartan-6, and Artix-7, along with embedded communication protocols like UART, SPI, CAN, and AMBA.

Through her dedication to skill development and industry-oriented training, Ms. Kanchana has played a significant role in bridging the gap between academic learning and industry requirements.

Address:Subject Matter Expert, Corporate Trainer for Embedded Systems and VLSI Design, Cranes Varsity, Bangalore, Karnataka, India, 560011




Agenda

Day 1 – 11 March 2026

Time Session Activity
9:15 AM – 9:40 AM Inauguration Opening Ceremony
9:40 AM – 11:15 AM Session 1 Technical Session
11:15 AM – 11:30 AM Break Tea Break
11:30 AM – 1:30 PM Session 2 Technical Session
1:30 PM – 2:00 PM Break Lunch Break
2:00 PM – 4:00 PM Session 3 Hands-on / Technical Session

Day 2 – 12 March 2026

Time Session Activity
9:15 AM – 11:15 AM Session 4 Technical Session
11:15 AM – 11:30 AM Break Tea Break
11:30 AM – 1:30 PM Session 5 Technical Session
1:30 PM – 2:00 PM Break Lunch Break
2:00 PM – 3:00 PM Session 6 Technical Session / Wrap-up


Organized by:
IEEE Student Branch MRIT & IEEE ComSoc Student Branch Chapter

Sponsered by:
IEEE Young Professionals (STEP Funding), IEEE Founadation

 


  Media

Chip craft-2026 brochure 406.79 KiB
chip craft-2026 banner 316.22 KiB
chip_craft_agenda 469.18 KiB