Durga Misra

The IEEE Electron Device Society is celebrating 100 years of the Field Effect Transistor (FET) in 2025-2026. During the past century, innovations of the FET have contributed to many applications, including computing and communications. The contribution of dielectrics to FET’s development is highly significant. Historically, SiO₂ was the main driver of MOSFETs as the transistor’s gate dielectric. Once the thickness of SiO₂ reached the onset of direct tunneling region (<1.5 nm), HfO₂-based high-k insulators were introduced to suppress leakage current. Several applications of high-k dielectrics have emerged, including ferroelectric FETs and resistive random-access memory (RRAM) devices that are being investigated for possible implementation in systems with artificial intelligence hardware. The electrical performance in these devices depends on the dielectric deposition process, precise selection of deposition parameters, pre-deposition surface treatments, and subsequent thermal budget.

Biography:

Prof. Durga Misra is a Professor and Chair of the Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, USA. His current research interests are in the areas of nanoelectronics devices and circuits, especially in nanometer CMOS gate stacks and switching devices. He is Fellow of IEEE and a Distinguished Lecturer of IEEE EDS. He is, also a Fellow of the Electrochemical Society (ECS). He received the Thomas Collinan Award from the Dielectric Science & Technology Division and the Electronic and Photonic Division Award from ECS. He has published more than 200 technical articles in peer reviewed Journals and in International Conference proceedings including more than 100 Invited Talks. He received the M.S. and Ph.D. degrees in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1985 and 1988, respectively.

Fernando Guarín

The patent for the Field-Effect Transistor (FET) dates to 1925, and the first successful demonstration of the point-contact transistor occurred in 1947. These groundbreaking inventions, combined with rapid advances in materials, device integration, layout design, automated design tools, and semiconductor processing, have fueled the exponential growth of the semiconductor industry. Over the past seven decades, this growth has shaped the environment, research infrastructure, supplier ecosystem, and technological innovations that have transformed our world. Modern society relies on semiconductors for nearly every aspect of daily life. Looking ahead, we are poised to see Artificial Intelligence AI, increased instrumentation, with ever-growing data volumes and the intelligence to process and communicate this data. The rise of the Internet of Things (IoT) and the continued rollout of 5G/6G will accelerate progress, driving industries and society to operate at unprecedented speeds. These advances have already made the world "smaller and flatter," creating a globally integrated environment full of both opportunities and challenges. The vast amounts of information generated now offer a unique path to addressing some of the most pressing problems facing the world today.

In this talk, we will offer a historical overview of the transistor's invention and key milestones in semiconductor technology development. We will also examine the current economics and supply chain behind semiconductor production, focusing on the roles and interactions of Pure Play Foundries, Integrated Device Manufacturers, and Fabless companies. Additionally, we will explore the broader implications for the planet, from geopolitical dynamics to global challenges related to sustainability and survival. Finally, we will discuss major trends in the semiconductor industry and the role of government incentives in the U.S., Europe, China, Korea, Japan, and India.

Biography:

Dr. Fernando Guarin retired as a Distinguished Member of Technical Staff at Global Foundries in East Fishkill, New York, where he led the reliability team responsible for the qualification of 5G technologies. In 2015, he retired from IBM’s Semiconductor Division after 27 years as a Senior Member of Technical Staff.  He earned his BSEE from the “Pontificia Universidad Javeriana”, in Bogotá, Colombia, the M.S.E.E. degree from the University of Arizona, and the Ph.D. in Electrical Engineering from Columbia University, NY.  He has worked in microelectronic reliability for over 42 years.

 From 1980 until 1988, he worked in the Military and Aerospace Operations division of National Semiconductor Corporation.  In 1988, he joined IBM’s microelectronics division, where he worked in the reliability physics and modeling of Advanced Bipolar, CMOS, and Silicon Germanium BiCMOS technologies. Most recently, he was the leader of the team qualifying GlobalFoundries RF 5G technology offerings.

Dr. Guarín is an IEEE Life Fellow, Distinguished Lecturer for the IEEE Electron Device Society EDS, where he has served in many capacities, including member of the IEEE’s EDS Board of Governors, chair of the EDS Education Committee, and Secretary for EDS. He was the EDS President 2018-2019. He is the 2026=2027 Division I Director for IEEE.

Imran Bashir

Electrical engineers are essential to the development of quantum computers because qubits are passive devices that must be driven, read out, and stabilized by sophisticated classical electronics. Achieving large-scale systems will require control and measurement circuits that are low power, high speed, low noise, and highly integrated. Yet many circuit designers and microwave engineers are unaware of the impact their expertise can have in this field, and may lack familiarity with quantum-computing fundamentals and with qubit–circuit interactions. This tutorial aims to bridge that gap by translating key concepts from quantum mechanics into an engineer-friendly framework. It provides an overview of qubit operations and the role of control electronics, with a focus on silicon qubits and the associated classical control, readout, and detector circuits.

Biography:

Imran Bashir (SM’99) received the B.S.E.E. (summa cum laude) degree from the University of Texas at Arlington in 2001 and the M.S.E.E. and Ph.D. degrees from the University of Texas at Dallas in 2008 and 2014. He joined Texas Instruments in 2002 and was elected to the prestigious title of Group Member of Technical Staff in 2006. He played a key role in the productization of GSM/EDGE SoCs based on the Digital RF Processor DRPTM technology. In 2009, he joined NVidia Inc. and worked on 2G/3G/4G multi-mode cellular radios. In 2014, he worked as a Mixed Signal IC Designer with a start-up called Senseeker Engineering Inc., where he designed read-out circuits for IR image sensors. During the Fall of 2015, he was a Senior Research Fellow at the School of Electrical and Electronic Engineering at University College Dublin (UCD), Dublin, Ireland. In 2016, he joined Cypress Semiconductor Corp. as an RF/Analog IC design engineer working on connectivity ICs. From 2019 to 2025, Imran was at Equal1 Labs Inc., where he was the VP of Analog Engineering, a silicon qubit startup. Imran recently joined Quantinuum, where he is working on highly integrated and scalable cryogenic electronics for trapped ions-based Quantum Processors. Imran has multiple patents and conference papers in the field of Digital Polar Transmitters, Injection Locked Oscillators, and Cryogenic Electronics for Quantum Processors. In addition to his day-time job, Imran has volunteered as an officer for the IEEE-SSCS, IEEE-CASS, and IEEE-EDS Santa Clara Valley Chapters. He is also a member of Tau Beta Pi (TBP) and Eta Kappa Nu (HKN)

Mukta Farooq

While silicon scaling has reached astonishing levels over the last half century, there has not been a corresponding level of scaling in electronic packaging technology. However, Artificial Intelligence (AI) architectures are now changing the landscape, increasingly moving us towards chiplets and advanced packaging technology, especially Heterogeneous Integration (HI). What are these unique requirements of AI which are driving the need for HI? What are some of the unique challenges in semiconductor and packaging technologies that must be overcome to make this successful? This seminar will discuss key HI methods including interposers, fan out wafer level processing, silicon bridges, and 3D integration. We will look at their attributes as well as their challenges, to determine how they can be leveraged to achieve AI architectures

Biography:

Dr. Mukta Farooq is a Distinguished Research Scientist at IBM Research, with expertise in 2.5D / 3D wafer integration and packaging, Cu TSV integration in CMOS wafers, lead-free C4 and micro-bump technology, and reliability of stacked-die modules. She currently leads the AI HW Center’s Heterogeneous Integration Project. Mukta has 248 granted US Patents, several Top 10% and Top 25% Patent Awards from IBM and is an IBM Master Inventor. She has written seminal papers on 3D integration, taught workshops and short courses at IEDM, VLSI, EDTM, etc.

Mukta is an IEEE Fellow, a Distinguished Lecturer of the Electron Devices Society and recipient of the 2023 IEEE EDS J.J. Ebers Award. She is an active mentor to several professionals, chairs the Mid-Hudson EPS and EDS chapters, and is a champion of technical vitality at IBM. Mukta is a Distinguished Alumna of the Indian Institute of Technology – Bombay. She earned her B.S. from IIT Bombay, M.S. from Northwestern University, and Ph.D. from Rensselaer Polytechnic Institute in Materials Science and Engineering.

Marko Radosavljevic

Transistor scaling has been one of the key engines driving the semiconductor industry for many decades now. Beyond traditional (Dennard) scaling of physical dimensions and supply voltages, innovations such as new materials and new architectures are being constantly and regularly deployed to enable the introduction of new technology nodes.

In this presentation, I will provide a general overview of the next big architecture change, which is commonly pursued across industry, consortia, and academia: monolithic 3D integration. This option is demonstrated to be a platform on which further logic advances will build. I shall discuss building blocks of such technology, potential benefits it will unleash, as well as key current experimental status. Finally, I will extend the discussion by using an example of power delivery to demonstrate the relevance of technologies developed in the context of logic scaling to other semiconductor applications.

Biography:

Marko Radosavljević is a Full Professor in the Department of Electrical Engineering at the University of Notre Dame, which he joined in January of 2026. He received a PhD in physics from the University of Pennsylvania in 2001, followed by 2 years as a postdoc at IBM T.J. Watson Research Center in New York. In 2003, he joined the Components Research (CR) division of Intel Corporation in Oregon. Marko’s research has been focused on non-Si transistors, such as InP, InSb, GaN material families, as well as carbon nanotubes for applications in logic, RF and power delivery. Between 2019 and 2025, he led a monolithic 3D integration group in CR, enabling new functionalities and providing ultimate transistor density improvements. He is a senior member of IEEE and serves the community as editor of IEEE Transactions of Materials for Electron Devices after serving as editor of EDL and committee member for the IEDM conference.

Sreeram Sundaresh

As semiconductor manufacturing enters the sub-2 nm/Ångström era, increasing process complexity, variability, and data volume are pushing conventional control methods to their limits. Modern fabs generate massive, high-dimensional datasets from equipment sensors, metrology, and process logs—creating a strong foundation for AI-driven smart manufacturing.

This talk explores how machine learning and physics-informed models are transforming semiconductor fabs from reactive systems into predictive and adaptive environments. Key applications include advanced Fault Detection and Classification (FDC), Virtual Metrology (VM) for real-time process estimation, and AI-enhanced Run-to-Run (R2R) control for dynamic recipe optimization. Additional focus is placed on cross-module yield learning, predictive maintenance, and AI-based defect inspection, all of which significantly improve yield, throughput, and operational efficiency.

We also address critical deployment challenges such as data quality, model generalization, interpretability, and integration with legacy manufacturing systems. The session concludes with a forward-looking perspective on digital twins and autonomous fabs, where AI enables real-time, self-optimizing semiconductor manufacturing.

Biography:

Sreeram Sundaresh previously worked as a module development engineer at Intel Corporation, where his work was focused on development of etch stop materials. He received his doctoral degree in electrical engineering from the University of Central Florida in 2023, where his research focused on the process optimization and characterization of p-type copper based delafossite transparent conducting thin films and their applications. He also holds a master’s degree in electrical engineering from UCF and a bachelor’s degree in electronics and telecommunication engineering from the University of Mumbai, India.

His expertise lies in semiconductor processing, thin film deposition, and material characterization, with proficiency in techniques such as photolithography, RF sputtering, plasma deposition and electrical transport measurements. Throughout his academic and professional career, he has contributed extensively to research in semiconductor materials, publishing more than 14 peer-reviewed papers in esteemed journals such as the ECS Journal of Solid-State Science and Technology and Coatings