Dr. Salvador Ivan Garduño Vértiz received his Ph.D. degree in electrical engineering from the Center for Research and Advanced Studies (Cinvestav) in 2012. He has been a professor in the field of semiconductor devices at the Autonomous University of the State of Hidalgo, Mexico. He is currently a Research Fellow supported by SECIHTI at CINVESTAV-IPN, where he conducts research in semiconductor devices and microelectronics. His work focuses on the fabrication, modeling, and characterization of semiconductor devices, including thin-film transistors and MOSFET-based technologies. He is an IEEE Senior Member.
FET100 Bootcamp 2026: Electronic Circuit Design & Chip Development
#EDS
#CINVESTAV
#FET100
#OpenSilicon
IEEE Electron Devices Society (EDS)
Second Mexico Technical Meeting 2026 (MTM_02-2026)
FET100 Celebration | IEEE Open Silicon Initiative
Mexico Chapter and Cinvestav Zacatenco Student Branch Chapter
Center for Research and Advanced Studies of the National Polytechnic Institute, Mexico
The IEEE Electron Devices Society (EDS) Student Chapter at Cinvestav invites you to participate in this three-day technical bootcamp, organized in collaboration with the Solid-State Electronics Section (SEES) and aligned with the IEEE FET100 celebration and the IEEE Open Silicon Initiative.
The event focuses on semiconductor devices and integrated circuit design, combining lectures and hands-on activities.
Date and Time
Location
Hosts
Registration
-
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- Avenida Instituto Politécnico Nacional 2508
- Colonia San Pedro Zacatenco, Miguel Bernard La Escalera
- Mexico City, Mexico
- Mexico 07360
- Building: Cinvestav, SEES
- Contact Event Hosts
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Ariel Alejandro Fernández Pirez, Eng. ; ariel.fernandez.p@cinvestav.mx;
Salvador Ivan Garduño, PhD. ; sgarduno@cinvestav.mx;
Anisleidy Broche Forte, Eng. ; anisley.broche96@gmail.com
- Co-sponsored by Department of Electrical Engineering – Section of Solid-State Electronics (SEES), Cinvestav, Mexico
- Starts 23 March 2026 03:00 PM UTC
- Ends 28 March 2026 03:00 AM UTC
- No Admission Charge
Speakers
Dr. Ivan of SECIHTI-Cinvestav SEES
Topic:
Fundamentals of FET Devices
• Introduction to FET Devices and Their Historical Development
• Fundamentals of MOSFET Physics and Operation
Biography:
Email:
Address:Distrito Federal, Mexico
Dr Yoanlys of Cinvestav-SEES
Topic:
Device Simulation and IC Design Fundamentals
• TCAD Simulation of MOSFET Devices with Silvaco (Process and Device Simulation)
• Fundamentals of IC Design with MOS Technology
• Introduction to Open-Source Tools for IC Design
Biography:
Dr. Yoanlys Hernández Barrios received a Ph.D. degree in electrical engineering from the Center for Research and Advanced Studies (Cinvestav) in 2020. From 2021 to 2025, he held a research associate position at the Institute of Microelectronics at TU Wien in Vienna, Austria. Since 2025, he has been a Full Research Professor at CINVESTAV. His area of expertise is focused on TCAD simulation, compact modelling implementation, and reliability analysis of semiconductor devices and circuits, as well as IC design, including open source and commercial tools. He is an IEEE Member.
Email:
Address:Distrito Federal, Mexico
Dr Benito of InnovaBienestar-Kutsari
Topic:
Digital IC Design and Implementation
• Full ASIC Design Flow (RTL Design, Verification, Physical Design)
• Guided Project: From Verilog to Chip Fabrication (Open Silicon Initiative)
• Closing Discussion and Networking Session
Biography:
Dr. Benito Granados Rojas is a specialist in CMOS integrated circuit design and currently serves as a consultant at the Kutsari National Center for Semiconductor Design. His work focuses on the design, simulation, and verification of analog and digital integrated circuits, as well as on the development of CMOS-based microsystems, including CMOS-MEMS devices and floating-gate MOS (FGMOS) technologies. He has experience in the complete design flow, from device-level considerations to circuit implementation and optimization. In addition, he is actively involved in the training of human resources in microelectronics and integrated circuit design.
Email:
Address:Distrito Federal, Mexico
Dr. José of Cinvestav-SEES
Topic:
Introduction to MOS Fabrication Processes
- Metallization Process in MOS Fabrication
- Photolithography Techniques and Patterning
Biography:
Dr. José Guadalupe Sánchez López received a Ph.D. degree in Nanosystems, Bioengineering and Energy Technologies from Rovira i Virgili University (URV), Spain, in 2018. From 2019 to 2025, he held a research associate position at the Institute of Chemical Research of Catalonia (ICIQ), Spain. Since 2025, he has been a Full Research Professor at the Center for Research and Advanced Studies (CINVESTAV), Mexico. His work focuses on materials science, solid-state physics, and nanotechnology to address challenges in the efficiency and stability of semiconductor devices. He is an IEEE-EDS Member.
Email:
Address:Distrito Federal, Mexico
Agenda
MTM_02-2026 is an IEEE EDS-sponsored technical meeting, organized as part of the FET100 celebration. It is co-sponsored by the Solid-State Electronics Section (SEES) at the Center for Research and Advanced Studies of the National Polytechnic Institute (Cinvestav) and aligned with the IEEE Open Silicon Initiative.
Media
| FET100 Bootcamp 2026 at CINVESTAV-SEES, Mexico City | Participants had the opportunity to develop real chip designs through a hands-on chip design experience. | 1.43 MiB |