Fundamental Insights into Channel and Gate Engineered Double Gate Junction-Less Transistor

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IEEE Electron Devices Society IIT Roorkee chapter is organising a Distinguished Lecture by Prof. Manoj Saxena. He is currently a Professor in the Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India. His research areas are Mathematical Modeling and TCAD Simulation of Non-Classical MOSFET, Tunnel FET, and HEMT designs. Currently, he is IEEE EDS Distinguished Lecturer and Chairman of the IEEE EDS Delhi Chapter.


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  • ECE Conference room
  • Roorkee, Uttaranchal
  • India 247667
  • Building: ECE Department
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Prof. Manoj of Deen Dayal Upadhyaya College, University of Delhi

Topic:

Fundamental Insights into Channel and Gate Engineered Double Gate Junction-Less Transistor

Abstract:

Scaling of the CMOS transistor design poses serious constrain to the electrostatic control of charge carriers in the channel region. This will adversely affect the device behaviour in terms of the severe short-channel effects (SCEs) such as threshold voltage roll-off and hot carrier effects. To overcome the significant problem associated with the nanoscale MOSFET architecture, double gate junctionless (DG-JL) transistor has emerged as a potential candidate. As the current flow is mainly concentrated at the centre of film, surface scattering is very less which increases mobility and hence current drive in Single Material Double Gate JL transistor. In order to improve the transconductance, on-state current and gate-controllability over the channel, Dual Material DG-JL Transistor design was proposed. In the present talk, I shall be focusing on development of analytical model of drain current for Dual Material DG-JL Transistor. In the later part of my talk, I shall be addressing the impact of Non-Uniform Doping on the Reliability of Double Gate JunctionLess Transistor.

Biography:

Biography:

Manoj Saxena received M. Sc., and Ph.D. in Electronics from the University of Delhi, New Delhi, in 2000 and 2006 respectively. He is currently a Professor in the Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India. He has authored or co-authored 375 technical papers in international journals and conference proceedings. His research areas are Mathematical Modeling and TCAD Simulation of Non-Classical MOSFET, Tunnel FET, and HEMT designs and has delivered 40+ IEEE EDS Distinguished Lectures. He is a Fellow of the National Academy of Sciences India (the oldest Science Academy of India); a Fellow-The Institution of Electronics and Telecommunication Engineers (IETE), India, Senior Member-IEEE, Member of the Institute of Physics (UK), and Member of Institution of Engineering and Technology (IET), UK. In past he has served IEEE in different capacities i.e. Vice-Chair– IEEE Electron Device Society (EDS) SRC Region 10 (2015-2017); Secretary - IEEE Delhi Section (2019; EDS Newsletter Regional Editor of South East Asia (2015-2020); Member of the IEEE EDS Board of Governor (2018-2021, 2021 - 2023); Associate Editor-in-Chief of the IEEE EDS Newsletter (2021 - 2023). Currently, he is IEEE EDS Distinguished Lecturer (2016-) and Chairman of the IEEE EDS Delhi Chapter (2022 – till date).

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