Robert Ashton Ph.D.

The electrostatic shock you feel on your finger when reaching for a doorknob on a cold dry day is more than an annoyance. It has long been a challenge in the manufacture of electronic systems. This talk will discuss why electrostatic discharge (ESD) is a threat during electronics manufacturing. It will then discuss how the electronics industry deals with the threat with a three-pronged approach. Manufacturing facilities are designed and run in a manner to reduce the prevalence of ESD. integrated circuits are designed to have specified levels of robustness to ESD threats. Integrated circuits are then stress tested to ensure the products have the robustness they are designed to have. The ESD challenge is, however, getting more difficult as the industry moves to more advanced technologies, higher data rates and increasing levels of integration, especially with the move to 2.5D and 3D integration.

Biography:

Robert received BS and Ph.D. degrees from the University of Rhode Island in Physics, studying the flow properties of Superfluid Liquid Helium 4. He has held post-doctoral positions at Rutgers University and Ohio State University. He joined AT&T Bell Laboratories in their integrated circuit technology development area and stayed with that division through their spin-offs to Lucent Technologies Bell Laboratories and Agere Systems. While at Bell Laboratories among his responsibilities was liaison with the ESD design team. To support this activity, he built a transmission line pulse measurement system to measure the properties of integrated circuit components in the ESD time and current regime. This activity led him to become involved in the Electrostatic Discharge Association (ESDA) and JEDEC ESD and latch-up test standards working groups. After leaving Agere Systems he joined White Mountain Labs in Phoenix, a provider of ESD and latch-up testing services. He then joined ON Semiconductor (now onsemi) in their protection products division. Since retirement he has remained active in ESDA and JEDEC ESD and latch-up testing standards working groups. In retirement he wrote a blog on ESD testing for Minotaur Labs, a provider of ESD and latch-up testing.  He received the 2013 outstanding volunteer award from ESDA and the ESDA Joel P. Weidendorf Memorial Award for contributions in the field of EOS/ESD Standards development. Robert was on the Steering Committee for the IEEE Conference on Microelectronic Test Structures and was Technical Chairman in 1994 and General Chairman in 1997. He has published numerous technical papers as a lead or co-author on integrated circuit test structures and ESD protection and testing. He has presented tutorials on ESD and latch-up testing at the IEEE Conference on Microelectronic Test Structures and the EOS/ESD Symposium. Robert is an IEEE Senior and Life Member.

Email:

Address:Arizona, United States, 85045