Antonio Liscidini of University of Toronto

In this talk, we’ll delve into some fundamental aspects of signal processing to understand how they will shape the future of IC mixed-signal design. In the first part of the lecture, we’ll compare power efficiency and technology evolution, discussing the dualism of analog/digital and voltage/time in terms of signal processing and dynamic range achievable. In the second part of the presentation, we’ll explore two examples of how analog mixed-signal can achieve the flexibility of digital signal processing while maintaining higher speed and power efficiency of analog. We’ll present a novel topology of a MAC analog accelerator for digital computation in AI and a quantized analog TX for 5G wireless communication that exploits a power-scalable band-pass RF DAC. These solutions outperform the state of the art and suggest new directions for future development in mixed-signal computation and software-defined analog front-ends.

Biography:

Antonio Liscidini received a Laurea (summa cum laude) and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 2002 and 2006, respectively. He was a summer Intern with National Semiconductors, Santa Clara, CA, USA, in 2003, studying polyphase filters and CMOS low-noise amplifiers. From 2008 to 2012, he was an Assistant Professor with the University of Pavia and a consultant with Marvell Semiconductors, Pavia, in the area of integrated circuit design. In 2012, he moved to the Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada, where he is currently Full Professor and Associate Chair Graduate. From 2019 to 2022 he was consultant for Huawei Technology Group in the area of RFIC for optical communication and SerDes. Since 2022 has been consultant for Marvell Technology group. His research interests are focused on analog mixed signal interfaces with particular emphasis on the implementations of transceivers and frequency synthesizers for wireless-wireline communication and ultra-low power applications.

Dr. Liscidini was a recipient of the Best Student Paper Award at the IEEE 2005 Symposium on VLSI Circuits, co-recipient of the Best Invited Paper Award at the 2011 IEEE CICC and Best Student Paper Award at the 2018 IEEE ESSCIRC.

He is currently Associate Editor in Chief for IEEE Transactions on Circuits and Systems II: Express Briefs and Associate and IEEE Solid State Circuit Letters. He has served as an Associate Editor for Editor for IEEE Open Journal of Solid-State Circuit Society, IEEE Transactions on Circuits and Systems II: Express Briefs (2008-2011) (2017- 2018) and as a Guest Editor for the IEEE Journal of Solid-State Circuits (2013) (2016) and IEEE RFIC Virtual Journal (2018). He has been member for many conferences including ISSCC, ESSCIRC, and CICC. Between 2016 and 2018, he has been a Distinguished Lecturer of the IEEE Solid-State Circuits Society. Since 2026, he is a IEEE Fellow.

Davide Tonietto of Huawei Technologies

Explosive computing growth fueled by the AI revolution is putting enormous pressure on energy efficiency. As number of cores and connection bandwidth increases exponentially, serial links are becoming the #1 energy expenditure. It is estimated that serial links consume between 30% and 60% of the total computing & switching power. Besides being an overall energy consumption problem, this brings a variety of architectural challenges, such as the power delivery and heat dissipation management. 

Part 1: The basics of serial link efficiency

What is serial link efficiency? What does it depend on? Is it actually improving? Is it better to go wide-slow or narrow-fast? Does it always pay off to reduce the number of “hops” in a link? I will explain in the simplest terms why I think it is time for a drastic change in what we do to increase interconnect bandwidth and why commonly talked about approaches to improve efficiency will not work as well as advertised. To understand efficiency, we have to dig deep into SerDes historical evolution and how various factors affected efficiency and complexity and how they are related. 

Part 2: SerDes power scaling

One of the reasons contributing to the rapid increase of serial link power consumption is the inability of most SerDes to adapt significantly their power consumption to the requirements of the channel they operate on. Most ASICs are built with only one type of long reach (LR) SerDes on die but in a real system they will operate on a vast variety of backplane, chip to chip or chip to module links that vary enormously in complexity from XSR (Extra Short Reach) to VSR (Very Short Reach) to LR. However, most SerDes can only marginally adjust their consumption and this is achieved by a static, manual and error prone process. Therefore, most links use more energy than necessary. I will present a fully automatic power management system that can dynamically reduce a DSP based LR SerDes consumption in excess of 50% depending on channel requirements.

Biography:

Davide Tonietto is Huawei Fellow & Founder of Hisilicon Serial Link Team (A.K.A. HiLink), with Huawei Technologies Canada since 2011. He was responsible for Hisilicon SerDes IP technology roadmap definition, execution and integration from 2011 to 2021. Over this period of time his organization provided SerDes for over 200 high performance ASICs with data rates ranging from 10 to 112Gbps for applications in Networking, DC, AI, HPC, Wireless infrastructure and Mobile. He holds more than 20 US patents and co-authored several papers on SerDes and wireline communication. His current focus is on improving interconnect efficiency by increasing parallelism, flexibility and decreasing data rate and complexity.