The Road to Gate-All-Around CMOS
The IEEE Solid-State Circuits Society (SSCS) Student Branch Chapter at Oregon State University hosted a Distinguished Lecturer talk by Alvin Loke, Senior Principal Engineer at Intel, on April 21, 2026.
The lecture, titled “The Road to Gate-All-Around CMOS,” provided an in-depth overview of the evolution of CMOS technology and its continued scaling in advanced technology nodes.
Date and Time
Location
Hosts
Registration
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- Oregon State University
- Corvallis, Oregon
- United States
- Building: Kelley Engineering Center (KEC)
- Room Number: 1001
Speakers
Alvin Loke
The Road to Gate-All-Around CMOS
Biography:
Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel’s gate-all-around CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. Alvin received a BASc from the University of British Columbia, and an MS and PhD from Stanford. After several years in CMOS process integration, he has since worked on analog/mixed-signal design, focusing on a variety of wireline links, including chiplet IOs, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary, SSCS Global Chapters Chair, and again as SSCS Distinguished Lecturer. Alvin frequently speaks on CMOS technology and its impact on analog design, having authored invited publications including the CICC 2018 Best Paper and short courses at ISSCC, VLSI Symposium, CICC, and BCICTS. His publications have received over 1900 citations to date.
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