Prof. Hanumolu

Multi-phase, low-noise clock synthesizers are critical for high-speed serial transceivers. While LC-based PLLs are traditionally used, scaling to multi-lane systems and generating multiple phases presents significant challenges. Ring oscillators naturally provide multi-phase outputs but suffer from limited phase accuracy and high supply sensitivity, especially beyond 10 GHz. In this seminar, we present techniques to improve the phase noise and supply-noise immunity of RO-based PLLs operating above 10 GHz. These include a type-III supply-regulated architecture to extend the tuning range and suppress supply sensitivity, as well as feedforward frequency multiplication, enabling >25 GHz synthesis from ring oscillators. Experimental results from prototype PLLs fabricated in Intel 16 demonstrate the effectiveness of these approaches.

Biography:

Pavan Hanumolu is a Professor in the Department of Electrical and Computer Engineering at the University of Illinois, Urbana-Champaign. His research interests include energy-efficient integrated-circuit implementations of wireline communication systems. Pavan served as Editor-in-Chief of the IEEE Journal of Solid-State Circuits from 2019 to 2022 and is an IEEE Fellow.

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