[Legacy Report] From Deep Trenches to Skyscrapers: A walk down Memory Lane

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Memory technology and the memory business has for many years been the engine that powered technological innovations in the semiconductors especially in the area of lithography and innovative micro-structural engineering. While stand-alone memory itself has been commoditized, when embedded in high performance logic it provides incredible leverage for high performance processors, network and mobile appliances, and almost every application. In this talk, we will explore the course of memory in systems, especially DRAM, integration of deep trench technology into high performance logic, the value it brings as well as the collateral advantages it has brought about in power management, noise decoupling, autonomic chip repair and its potential evolution into 3-dimensional chip technology.
About the Speaker
Subramanian S. Iyer is a Distinguished Engineer and Chief Technologist for the Semiconductor Research and Development Center, IBM Systems & Technology Group, and is responsible for technology development strategy, embedded memory and 3 Dimensional Integration. Until recently he was Director of 45nm CMOS Development. He obtained his B.Tech in Electrical Engineering at the Indian Institute of Technology, Bombay, and his MS and PhD in Electrical Engineering at the University of California at Los Angeles. He joined the IBM T. J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group till 1994, when he founded SiBond LLC to develop and manufacture Silicon-on-insulator materials. He has been with the IBM Microelectronics Division since 1997. Dr. Iyer has received two Corporate awards and four Outstanding Technical Achievement awards at IBM for the development of the Titanium Salicide process, the fabrication of the first SiGe Heterojunction Bipolar Transistor , the development of embedded DRAM technology and the development of eFUSE technology. His current technical interests and work lie in the area of 3-dimensional integration for memory sub-systems and the semiconductor roadmap at 22nm and beyond. He holds over 40 patents and has received 22 Invention Plateau awards at IBM and is a Master Inventor. He received the Distinguished Alumnus award from the Indian Institute of Technology, Bombay in 2004. Dr. Iyer has authored over 150 articles in technical journals and several book chapters and co-edited a book on bonded SOI. He has served as an Adjunct Professor of Electrical Engineering at Columbia University, NY. Dr. Iyer is a Fellow of IEEE and a Distinguished Lecturer of the IEEE and Chair of the mid-Hudson chapter of the Electron Device Society.

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