While digital Integrated Circuits (IC) have been reaping the benefits of CMOS technology scaling in terms of speed, power consumption, and area, the techniques used for analog signal processing have not progressed at the same rate. It is evident that there have been substantial and ongoing improvements in the performance of digital circuits when compared to analog building blocks. To address this disparity, there is a growing trend towards exploring alternative IC design strategies that leverage digital-in-concept methodologies to implement analog functions. By capitalizing on the well-established fullyautomated EDA digital tools, reimagining analog functions in digital terms holds the promise of making Analog IC blocks more conducive to achieving energy efficiency and adapting to the shrinking feature sizes of new technologies. This presentation aims to showcase the current state-of-the-art digital-based analog building blocks, such as OTA, comparators, and converters, along with their impact on emerging applications and technologies. This shift in approach has the potential to revolutionize the field of analog signal processing and pave the way for undefined advancements in IC design. 

Pedro Toledo is a Staff Analog Design at Synopsys, Lisbon, where he works in the development of high-speed SerDes and equalization circuits in advanced CMOS technologies, including nanosheet, GAA, and FinFET. His work focuses on PHY building blocks for PCIe, USB, and MPHY interfaces, covering CTLE, DFE, CDR, LDO, and signaldetection circuits. He received the Ph.D. degree in Microelectronics from Politecnico di Torino, Italy, and the Federal University of Rio Grande do Sul (UFRGS), Brazil, where he graduated Summa Cum Laude. His research interests include DIGOTA architectures, ZTC/GZTC MOSFET modeling, low-voltage analog design, and digital-based analog processing. Dr. Toledo has authored numerous papers in IEEE journals and conferences and serves as reviewer for several IEEE Transactions and Letters. He is the recipient of multiple awards, including the SBMicro Best PhD Thesis Award, the IEEE ICECS Best Student Paper Award, and the YEF-ECE Best Paper Award. 

Joel Gak es miembro del IEEE desde 2007, recibió su doctorado en 2017 por la Universidad Nacional del Sur, Bahía Blanca, Argentina, recibió su Maestría y Grado en Ingeniería Electrónica de la Universidad Católica en 2010 y 2007 respectivamente. En 2005 se incorporó al Departamento de Ingeniería Eléctrica (Actualmente Departamento de Ingeniería) de la Universidad Católica, Montevideo, Uruguay. 

Charge-based memories, including SRAM, DRAM, and Flash, form the backbone of modern memory systems. Decades of technology scaling have enabled tremendous improvements in memory density, performance, and energy efficiency, supporting the storage and processing of data being generated at an unprecedented rate. The availability of these advanced memory technologies has also been a key enabler of the rapid growth of artificial intelligence. However, continued scaling is pushing conventional memory technologies toward their physical and geometric limits, creating an increasing need for new device concepts and architectures that can provide sustainable scaling paths toward higher density, improved performance, and greater energy efficiency. 

In this talk, we will discuss two representative emerging memory technologies: HfO₂-based ferroelectric memories and oxide-semiconductor-channel-based monolithic 3D DRAM. We will highlight recent advances in these technologies, examine their key device and integration challenges, and discuss their potenatial for future high-density memory systems. Beyond conventional data storage, we will further explore how these emerging memory technologies can enable compute-in-memory architectures to address the growing memory wall in AI computing. In particular, we will present their applications to key computational primitives, including matrix–vector multiplication accelerators and associative memories, illustrating opportunities to extend emerging memory technologies from high-density storage toward energy-efficient computing. 

Kai Ni received the B.S. degree in Electrical Engineering from University of Science and Technology of China, Hefei, China in 2011, and Ph.D. degree of Electrical Engineering from Vanderbilt University, Nashville, TN, USA in 2016 by working on characterization, modeling, and reliability of III-V MOSFETs. Since then, he became a postdoctoral associate at University of Notre Dame, working on ferroelectric devices for nonvolatile memory and novel computing paradigms. He is now an associate professor in University of Notre Dame since 2023 after joining Rochester Institute of Technology as an assistant professor. He has around 200 publications in top journals and conference proceedings, including Nature Electronics, IEDM, VLSI Symposium, IRPS, EDL, etc. His current interests lie in nanoelectronic devices empowering unconventional computing, domain-specific accelerator, and memory technology.  

El Dr. Silva Cárdenas ha desarrollado proyectos de investigación en colaboración con instituciones de España, Francia, Japón, Brasil, Argentina, Uruguay y Colombia, además de universidades y centros peruanos. Su producción científica incluye más de 76 publicaciones, un libro, tres capítulos de libros y la coedición de dos volúmenes especializados. 

A lo largo de su carrera, el Dr. Silva Cárdenas ha contribuido activamente a la formación de nuevas generaciones de ingenieros dictando cursos de posgrado en universidades de España, Argentina, Brasil y Uruguay. Asimismo, fue presidente de la Sección Perú del IEEE (2009-2010) y es presidente fundador del Capítulo de Circuitos y Sistemas (CAS-IEEE Perú), reconocido en múltiples ocasiones a nivel regional y mundial.