Dr. Chakraborty

This talk covers practical challenges for the development of integrated system designs for next-generation quantum computing,
spanning integrated circuits, systems, and microwave engineering. Starting at the system level, it details the design considerations
for non-multiplexed, semi-autonomous, transmon qubit state controllers (QSC) implemented in 14 nm CMOS FinFET technology.
The QSC includes an augmented general-purpose digital processor supporting waveform generation and phase rotation operations,
combined with a low-power current-mode single-sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG).
The QSC generates control signals in its target 4.5 GHz to 5.5 GHz frequency range, with a measured SFDR > 50 dB over a 500
MHz signal bandwidth. With the controller operating in the 4 K stage of a cryostat and connected to a transmon qubit in the
cryostat's millikelvin stage, measured transmon T1 and T2 coherence times were 75.5 μs and 73 μs, comparable to results obtained
using conventional room-temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76 × 10−4 per Clifford
gate was measured, again comparable to room-temperature control results. The QSC's maximum RF output power is −18 dBm, and
power dissipation per qubit under active control is 23 mW. An improved low-power design version reaching half of this power will
also be presented, along with clocking solutions for large arrays.

Biography:

Sudipto Chakraborty received his B.Tech. from IIT Kharagpur in 1998 and his Ph.D. from Georgia Tech in 2002. He was with Texas
Instruments until 2016, designing low-power ICs for more than 10 product families across automotive, wireless, medical, and
microcontroller lines. Between 2017 and 2025 he led low-power circuit design for next-generation quantum computing applications at
IBM Research using nanometer CMOS. Since 2026 he has been Director of RF Engineering at Omni Design Technologies, an IP
startup working on wideband and broadband communications in CMOS FinFET technologies at 3 nm and beyond. He has authored or
co-authored more than 90 papers, two books, and 99 U.S. patents, has served on the technical program committees of ISSCC, CICC,
RFIC, and IMS, and is an IBM Master Inventor. He is an associate editor of TCAS-I, TCAS-II, and the CASS magazine, a Distinguished
Lecturer for IEEE MTT-S, CASS, and SSCS, and an IEEE Fellow.