Dr. Marcelo Pavanello of Instituto de Micro y Nanotecnología, CSIC Madrid, Spain

The aggressive scaling of MOSFET dimensions triggered the search for alternative solutions for the traditional planar transistors for future technological nodes. Also, the advent of Quantum Computing raised interest in the cryogenic operation of ultimate MOSFETs for interface circuits between Qubits and electronic systems. Planar and tridimensional MOSFETs operating with fully depleted (FD) body fabricated in Silicon-On-Insulator (SOI) substrates are among the technological solutions being widely investigated.
Triple-gate Ω-shaped MOSFETs with fin height and width of similar dimensions, in the order of 10-15nm, commonly referred to as nanowires (NWs) in the literature, are promising contenders. One key challenge in scaling down transistors is achieving high drive current density per footprint while simultaneously preserving the excellent electrostatics of nanometer-scale MuGFETs, which is crucial for mitigating short-channel effects. To address these scaling limitations, vertically stacked nanosheet transistors have attracted
considerable attention. By layering multiple channels on top of each other, it allows for a significant increase in the current level per unit area, without sacrificing the electrostatic integrity inherently provided by nanometric MuGFETs. The experimental demonstration of seven-level stacked gate-all-around (GAA) nanosheet transistors achieved significant performance enhancements in both digital and analog applications, surpassing single-level transistors with similar structural characteristics. Moreover, due to their nanometer-
scale channels, quantum transport can be observed in aggressively scaled nanowires at cryogenic temperatures. In this scenario, this talk will present and discuss the operation of planar and tridimensional MOSFETs, both single-level and stacked with up to seven levels, when exposed to cryogenic temperatures down to 4 K. Peculiarities of these devices while operating in the cryogenic regime, such as transconductance oscillations indicating carrier confinement and self-heating, will be presented.

Biography:

Biography:

Marcelo Antonio Pavanello received the Electrical Engineering degree from FEI University in 1993, receiving the award “Instituto de Engenharia” given for the best student among all the modalities of engineering programs offered at FEI. He received the M. Sc. and Ph. D. degrees in 1996 and 2000, respectively, in Electrical Engineering (Microelectronics) from University of São Paulo, Brazil. From August to December 1998, he was with Laboratoire de Microélectronique from Université Catholique de Louvain (UCL), Belgium, working in the fabrication and electrical characterization of novel channel-engineered Silicon-On-Insulator (SOI) transistors. From 2000 to 2002 he was with the Center of Semiconductor Components and Nanotechnologies, State University of Campinas, Brazil, where he worked as a post-doctoral researcher in the development of a CMOS n-well process. Since 2003 he joined FEI University where he is now Full Professor at Electrical Engineering Department. In 2008 he has been with UCL as a visiting professor. Dr. Pavanello is Senior member of The IEEE and Brazilian Microelectronics Society. He is also Research Associate to the National Council for Scientific Development (CNPq), Brazil. Since 2007 he serves as IEEE Electron Devices Society (EDS) Distinguished Lecturer and has been nominated to the Compact Modeling Technical Committee of EDS in 2018. He is author and co-author of more than 300 technical papers in peer-reviewed journals and conferences, and author/editor of 6 books. Dr. Pavanello coordinates several research projects fomented by Brazilian agencies like FAPESP, CNPq and Capes. He also supervised several Ph. D. dissertations, M. Sc. thesis and undergraduate projects in Electrical Engineering. His current interests are compact modeling, fabrication, electrical characterization and simulation of SOI CMOS transistors with multiple gate configurations and silicon nanowires; the wide temperature range of operation of semiconductor devices; the digital and analog operation of novel channel-engineered SOI devices and circuits.

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