One Week Workshop on RTL to GDS-II VLSI Design and Hardware Security for Trusted Memory Systems
IEEE Gujarat Section, IEEE Solid State Circuits and Electron Devices societies Gujarat Section along with the Dhirubhai Ambani University (formerly DA-IICT), Gandhinagar, Gujarat, India successfully organized a one-week workshop titled "๐๐๐ ๐ต๐ฐ ๐๐๐-๐๐: ๐๐๐๐ ๐๐ฆ๐ด๐ช๐จ๐ฏ ๐ข๐ฏ๐ฅ ๐๐ข๐ณ๐ฅ๐ธ๐ข๐ณ๐ฆ ๐๐ฆ๐ค๐ถ๐ณ๐ช๐ต๐บ ๐ง๐ฐ๐ณ ๐๐ณ๐ถ๐ด๐ต๐ฆ๐ฅ ๐๐ฆ๐ฎ๐ฐ๐ณ๐บ ๐๐บ๐ด๐ต๐ฆ๐ฎ๐ด" from 6th to 10th July 2026.
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- Dhirubhai Ambani University
- Gandhinagar, Gujarat
- India 382007
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- Co-sponsored by Anchor Institute Program, Dhirubhai Ambani University (DAU), Gandhinagar, Gujarat, India
Speakers
Yash of DAU Gandhinagar
RTL to GDS Design
Discussed Verilog HDL, FPGA and RTL to GDS design flow
Biography:
Dr. Yash Agrawal is faculty at Dhirubhai Ambani University Gandhinagar, Gujarat. His specialization includes VLSI on-chip interconnects, Network-on-chip (NoC), Flexible Electronics and Stretchable Interconnects, Image/Video Processing using VLSI Architectures, Circuit and System Design for Bio-medical Applications, Numerical techniques - FDTD for signal integrity analysis.
He has completed his PostDoc from University of Rennes, France and Ph.D. and M.Tech from NIT, Hamirpur, Himachal Pradesh, India.
Dr. Yash has been expert and distinguished guest at various places. He is chairing IEEE Education Activity, and Chair of IEEE EDS and SSCS societies, Gujarat section. He is Editorial board member and reviewer of several reputed Journals. He has organized several workshops and part of the organizing committee in various Trainings, Seminars, and Conferences. He has been the Chairman and awarded with best forum member of IETE, Nagpur Division. He has also been awarded First rank in various national and inter-college level competitions and paper presentations.
He has been awarded with prestigious IETE—K S Krishnan Memorial Award-2017 for the Best System Oriented research paper. He achieved third place in All India Mentor Graphics design contest held at Bangalore, India.
He has many government funded projects. He has several publications in Book Chapters of Springer, IGI, Journals including IEEE Transactions in Electromagnetic Compatibility, IEEE Transactions in Nanotechnology, Springer, Taylor and Francis and several national and international reputed Conferences. He is guiding several Ph.D. and M.Tech. students.
Email:
Address:1101, FB1, Dhirubhai Ambani University (DAU), Gandhinagar, Gujarat, India, 382007
Sreeja of DAU Gandhinagar
VLSI Testing
Discussed various aspect of Hardware Security in VLSI Design
Email:
Address:Dhirubhai Ambani University, Dhirubhai Ambani University (DAU), Gandhinagar, Gujarat, India, 382007
Gaurav of CEERI Pilani, Rajasthan
Open Source EDA Platforms
Gave exposure to open source EDA platforms
Address:CEERI Pilani, , Pilani, Rajasthan, India, 333031
Media
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| Event Pic (Group Photo) | Event Pic9 | 1.04 MiB |