Mr. Ashis Maitra of Senior Director, Network & Edge Silicon Engineering, Data Center Group, Intel

Agenda:

1. Communication & data center networks — A system-level big picture

2. RAN / vRAN / Cloud — how data navigates from users to cloud computing and back

3. Intel Xeon processors & SoCs in communication and data center networks

4. From system architecture to silicon — VLSI SoC design flows

5. AI everywhere - adoption in day2day work to improve efficiency

6. Connecting an IIT Kharagpur ECE student to industry roles and opportunities

7. What to learn today to become more effective tomorrow

Biography:

Mr. Ashis Maitra, M.Tech from IIT Kharagpur in 2000,  is a senior semiconductor engineering leader with 25+ years of experience in SoC design, physical design, timing, synthesis, and design methodology.

He has been with Intel Corporation since November 2013, currently serving as Sr. Director, NES: End-to-End SoC Design Manager & End-to-End Physical Design Convergence and Signoff Owner in Bengaluru. His responsibilities include managing end-to-end SoC design for client/edge-server products and driving physical-design convergence and signoff across network SoCs.

Previously, he spent about 5 years at Freescale Semiconductor (later acquired by NXP) as a Principal Staff Engineer, working on STA, constraints, synthesis, physical design, and methodology leadership for complex automotive and industrial SoCs.

Earlier, he spent over 7 years at TranSwitch, working across RTL design, verification, synthesis, STA, DFT, formal equivalence, and physical-design activities. Core expertise: SoC architecture & implementation, physical design, STA, synthesis, timing constraints, DFT, RTL/verification, design methodology, and end-to-end signoff.