While silicon scaling has reached astonishing levels over the last half century, there has not been a corresponding level of scaling in electronic packaging technology. However, Artificial Intelligence (AI) architectures are now changing the landscape, increasingly moving us towards chiplets and advanced packaging technology, especially Heterogeneous Integration (HI). What are these unique requirements of AI which are driving the need for HI? What are some of the unique challenges in semiconductor and packaging technologies that must be overcome to make this successful? This seminar will discuss key HI methods including interposers, fan out wafer level processing, silicon bridges, and 3D integration. We will look at their attributes as well as their challenges, to determine how they can be leveraged to achieve AI architectures

Dr. Mukta Farooq is a Distinguished Research Scientist at IBM Research, with expertise in 2.5D / 3D wafer integration and packaging, Cu TSV integration in CMOS wafers, lead-free C4 and micro-bump technology, and reliability of stacked-die modules. She currently leads the AI HW Center’s Heterogeneous Integration Project and is the Technology Leader for 2.5D/3D at IBM Research. Mukta has 265 granted US Patents, several Top 10% and Top 25% Patent Awards from IBM and is an IBM Master Inventor. She has written seminal papers on 3D integration, taught workshops and short courses at IEDM, VLSI, EDTM, etc.  

Mukta is an IEEE Fellow, a Distinguished Lecturer of the Electronic Packaging Society and recipient of the 2022 IEEE EPS Sustained Contribution Award and the 2023 IEEE EDS JJ Ebers Award. She is an active mentor to several professionals, chairs the Mid-Hudson EPS and EDS chapters, and is a champion of technical vitality at IBM. Mukta is a Distinguished Alumna of the Indian Institute of Technology – Bombay. She earned her B.S. from IIT Bombay, M.S. from Northwestern University, and Ph.D. from Rensselaer Polytechnic Institute in Materials Science and Engineering.