Model-based DSP with FPGAs
The IEEE North Jersey Section is pleased to offer 12 hours of training on the topic of “Model-Based DSP with FPGAsâ€. This is a course on the use of Simulink and Altera’s DSP Builder for the design of firmware and algorithms for Field Programmable Gate Arrays (FPGAs). It consists of 4 sessions -- two on-site at NJIT and 2 online (anymeeting.com). The course assumes that students have prior experience with Matlab and some with Simulink, the first session beginning with a review of Simulink. This is followed by instruction and examples of signal processing and system simulation. Registrants who elect to purchase the Terasic DE0-Nano, the FPGA development platform (pictured) on which labs will be performed, will receive these platforms at the first session. All registrants will receive Altera’s Quartus II FPGA development software and DSP Builder. These are fully functional licenses that will be active for 2 months, provided free of charge courtesy of Altera. Two on-line sessions will cover the design flow for VHDL generation using Simulink and DSP Builder, the first covering the DSP Builder Standard Blockset and the second the Advanced Blockset. Hardware-in-the-Loop (HIL) simulation testing will be covered in the latter. Finally, at the 2nd on-site session students will work laboratory experiments on their FPGA development platform. Labs are to include (1) the design and implementation of a FIR filter, (2) build of a Digital Down-Converter (DDC), and (3) build of a QPSK baseband transceiver. Students may share a platform if desired when working the labs. Homework assignments will be provided, and solutions including m-code and Simulink models will be distributed, as well as a printed hardcopy of the presentation slides.
Requirements: Students are required to provide their own laptop running Windows XP or 7, with the 64-bit or 32-bit versions of Matlab and Simulink installed. Acceptable versions include 2010a, 2010b, 2011a, 2011b, and 2012a. Although not required but recommended to take full advantage of the course -- Simulink Fixed Point is required to use the Advanced Blockset, and the Communications Blockset is used on some Simulink examples. Trial licenses may be available from the Mathworks.
Date and Time
Location
Hosts
Registration
- Date: 05 Jan 2013
- Time: 03:00 PM UTC to 07:00 PM UTC
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- 154 Summit St
- Newark, New Jersey
- United States
- Building: New Jersey Institute of Technology
- Room Number: Faculty Memorial Hall Rm 110
- Click here for Map
- Contact Event Host
- David Haessig 973 934 0659 (cell)
- Starts 22 November 2012 04:10 PM UTC
- Ends 19 December 2012 11:00 PM UTC
- 6 in-person spaces left!
- Admission fee ?
Speakers
David Haessig of BAE Systems
Model-based DSP with FPGAs
Biography: David Haessig is the Manager of Waveform Products at BAE Systems, Wayne NJ. His group is engaged in development of wireless communication, control, and avionics systems for military applications. He recently served as the technical lead in BAE’s development of the Wideband Networking Waveform (WNW). Dr. Haessig holds degrees in Mechanical Engineering from Lehigh University and in Electrical Engineering from New Jersey Institute of Technology. He is a senior member of IEEE and an Adjunct Professor at NJIT where he has taught courses in controls and mechatronics. He holds 4 patents in the area of inertial stabilization and has 24 technical and professional publications.
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Address:New Jersey, United States