“Overview of VLSI Front End Design and Verification”
The IEEE CAS/EDS chapter of IEEE Hyderabad Section is planning to conduct a workshop
series on VLSI design with monthly workshops on complete VLSI Design flow ranging from
topics related to Front End Design, Back End Design, Custom Design, Layout Design, Design
for Testability, EMI/EMC Design and other aspects. The workshops will be conducted by
Industry experts who are practicing engineers in their respective fields and will be able to
give first hand industry trends and information regarding job opportunities. This workshop
is targeted towards graduate, post graduate students, research scholars. Further, young
professionals and fresh graduates interested in improving their career opportunities in
field of VLSI Design will also benefit from this workshop.
Date and Time
Location
Hosts
Registration
- Date: 17 Mar 2018
- Time: 04:00 AM UTC to 10:00 AM UTC
-
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- Muffakham Jah College of Engineering and Technology
- Hyderabad, Andhra Pradesh
- India 500034
- Building: Block 4
- Room Number: Seminar Hall
- Starts 06 March 2018 01:29 AM UTC
- Ends 15 March 2018 01:29 AM UTC
- No Admission Charge
Speakers
Avinash Yadlapati
Front End VLSI Design
Biography:
Avinash Yadlapati has 17+ years of Industry Experience in the field of VLSI Design,
Verification and Implementation. He is currently associated with Mirafra Technologies
(www.mirafra.com). He is designated as “Senior Director” in the Semiconductor division
(VLSI) of Mirafra Technologies where he is handling the complete Delivery and Operations
happening at Hyderabad. He is having wide hands-on experience in the areas of RTL Design
& Coding, Functional and Gate-Level Verification, Synthesis, Static Timing Analysis, Design
For Test and good knowledge on the Physical Design Flow. He has worked earlier in
companies like Infosys Ltd, Cyient Ltd, Qualcomm, AMD, Synopsys and HCL Technologies.
Avinash Yadlapati holds an M.Tech (VLSI) from K L Deemed to be University, A.P., India
(www.kluniversity.in) and currently pursuing his Ph.D (VLSI) from the same university. His
topic of research is Low Power -Design for Test (DFT) Techniques. Apart from his technical
interests, he has a strong interest in social reforms and runs an educational trust for
economically backward students (especially working for uplifting Girl children). He has
strong passion for education and vision of creating a strong education system along with
good value system.
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