IEEE SSCS Oregon Chapter May Meeting and Seminar (In-Person)
IEEE SSCS Oregon Chapter May Meeting and Seminar
Join us for a (in-person) talk from IEEE Fellow Dr. Sriram Vangal on Wednesday, May 3rd. The seminar will be held in Room 315 on the 3rd floor of the PSU Engineering Building (1930 SW 4th Avenue, Portland, Oregon).
This event is in-person.
Topic:
Towards Energy-Efficient Computing
Abstract:
Today’s many-core SoC architectures in scaled CMOS process demand wide dynamic voltage-frequency operating range, spanning multi-threaded high-throughput near-threshold voltage (NTV) to single-threaded burst performance modes, as well as fine-grain multi-voltage design and spatio-temporal power management to deliver maximum performance under stringent thermal and energy constraints. Interconnect scaling bottlenecks, process-voltage-temperature variations and aging-induced degradation pose major challenges going forward. We present key design techniques for logic, memory and on-die interconnect networks that enable energy-efficient, variation-tolerant and resilient many-core SoC designs in nanoscale CMOS. On the other computing extreme, wireless sensor node (WSN) for IoT require internal IP optimizations, necessary to work in harmony with smart and fine-grain power management of different components of the WSN for achieving energy-neutral WSN systems. Energy efficiency continues to be the core design challenge for artificial intelligence (AI) hardware designers. This talk will highlight emerging trends towards realizing energy-efficient AI hardware.
Speaker Biography:
Sriram Vangal is a Principal Engineer with Intel Labs researching AI-driven, in-situ silicon anomaly detection approaches to improve silicon reliability. He joined Intel Corporation in 1995 and has played a lead role in Multi-core CPU development incorporating network-on-chip (NoC) architectures, and resilient, near-threshold voltage (NTV) computing research. He received the B.E. degree from Bangalore University, India, in 1993, the M.S. degree from the University of Nebraska, Lincoln, USA in 1995, and the Ph.D. degree from Linköping University, Sweden in 2007 – all in Electrical Engineering. Sriram has received two Intel Achievement Awards for his work, and an Intel Labs Gordon Moore Award. Sriram has served on the ISSCC Technology Directions subcommittee, ISSCC TPC, and as a special-issue editor for JSSC. Sriram is an IEEE Fellow, and has published over 50 conference and journal papers, authored three book chapters on high-performance NoCs and energy efficient NTV designs, and has over 45 patents issued, with several pending.
Date and Time
Location
Hosts
Registration
- Date: 04 May 2023
- Time: 01:00 AM UTC to 03:00 AM UTC
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- 1930 SW 4th Avenue
- Portland, Oregon
- United States 97201-5304
- Building: PSU Engineering Building
- Room Number: 315
- Starts 22 April 2023 11:00 PM UTC
- Ends 04 May 2023 01:00 AM UTC
- No Admission Charge
Speakers
Sriram Vangal
Towards Energy-Efficient Computing
Today’s many-core SoC architectures in scaled CMOS process demand wide dynamic voltage-frequency operating range, spanning multi-threaded high-throughput near-threshold voltage (NTV) to single-threaded burst performance modes, as well as fine-grain multi-voltage design and spatio-temporal power management to deliver maximum performance under stringent thermal and energy constraints. Interconnect scaling bottlenecks, process-voltage-temperature variations and aging-induced degradation pose major challenges going forward. We present key design techniques for logic, memory and on-die interconnect networks that enable energy-efficient, variation-tolerant and resilient many-core SoC designs in nanoscale CMOS. On the other computing extreme, wireless sensor node (WSN) for IoT require internal IP optimizations, necessary to work in harmony with smart and fine-grain power management of different components of the WSN for achieving energy-neutral WSN systems. Energy efficiency continues to be the core design challenge for artificial intelligence (AI) hardware designers. This talk will highlight emerging trends towards realizing energy-efficient AI hardware.
Biography:
Sriram Vangal is a Principal Engineer with Intel Labs researching AI-driven, in-situ silicon anomaly detection approaches to improve silicon reliability. He joined Intel Corporation in 1995 and has played a lead role in Multi-core CPU development incorporating network-on-chip (NoC) architectures, and resilient, near-threshold voltage (NTV) computing research. He received the B.E. degree from Bangalore University, India, in 1993, the M.S. degree from the University of Nebraska, Lincoln, USA in 1995, and the Ph.D. degree from Linköping University, Sweden in 2007 – all in Electrical Engineering. Sriram has received two Intel Achievement Awards for his work, and an Intel Labs Gordon Moore Award. Sriram has served on the ISSCC Technology Directions subcommittee, ISSCC TPC, and as a special-issue editor for JSSC. Sriram is an IEEE Fellow, and has published over 50 conference and journal papers, authored three book chapters on high-performance NoCs and energy efficient NTV designs, and has over 45 patents issued, with several pending.
Agenda
6:00pm - 8:00pm: Professional/Career Seminar