How Transistor Scaling Reshaped the PLL
The first papers about integrated PLLs appeared in late sixties, the circuits were of course designed in BJT technology, often including some external components. This block today is still a key element in communication circuits. Actually, in recent years thanks to MOS scaling, it is also one of the building block on which the designers’ creativity was most allow to run free. As a matter of fact the use of scaled MOS technology allowed the implementation of so-called digitally-intensive PLLs, in which several calibrations, for instance based on least-mean square technique running in background, improve most of the PLL performance, a solution that couldn't even be dreamed of, at the time of the first integrated PLLs. However, the designer must still have a strong knowledge of the key issues of analog IC design to exploit technology scaling, from this standpoint the situation is unchanged. The fundamental limits, mostly noise and power, then matching, non linearity, and also quantization in “digital” PLL, are still there. The talk will discuss these issues taking as an example some recent implementation of digitally-intensive PLLs, evidencing the advantages of this approach but also the limitations and trade-off.
Date and Time
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- Date: 06 Nov 2023
- Time: 11:00 PM UTC to 12:30 AM UTC
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- 10155 Pacific Heights Blvd
- San Diego, California
- United States
- Starts 23 October 2023 05:31 PM UTC
- Ends 06 November 2023 06:31 PM UTC
- No Admission Charge
Speakers
Prof. Carlo Samori
How Transistor Scaling Reshaped the PLL
The first papers about integrated PLLs appeared in late sixties, the circuits were of course designed in BJT technology, often including some external components. This block today is still a key element in communication circuits. Actually, in recent years thanks to MOS scaling, it is also one of the building block on which the designers’ creativity was most allow to run free. As a matter of fact the use of scaled MOS technology allowed the implementation of so-called digitally-intensive PLLs, in which several calibrations, for instance based on least-mean square technique running in background, improve most of the PLL performance, a solution that couldn't even be dreamed of, at the time of the first integrated PLLs. However, the designer must still have a strong knowledge of the key issues of analog IC design to exploit technology scaling, from this standpoint the situation is unchanged. The fundamental limits, mostly noise and power, then matching, non linearity, and also quantization in “digital” PLL, are still there. The talk will discuss these issues taking as an example some recent implementation of digitally-intensive PLLs, evidencing the advantages of this approach but also the limitations and trade-off.
Biography:
Carlo Samori (Fellow, IEEE) received the Laurea degree in electrical engineering and the Ph.D. degree in electronics and communications from the Politecnico di Milano, Milan, Italy, in 1992 and 1995, respectively. He is a currently a professor with the Politecnico di Milano. He has worked mainly in the area of design of integrated circuits for communications both in bipolar and in CMOS technology, in particular focusing on low-phase noise VCO and PLL architectures. From 1997 to 2002, he was a consultant with Bell Laboratories, Murray Hill, NJ, and has collaborated with several semiconductor companies in Europe and US. He is the coauthor of more that 100 papers in international journals and conferences. In 2007, he published the book Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press), as a coauthor. Dr. Samori served on the technical program committee for the IEEE International Solid-State Circuits Conference (ISSCC) and the European Solid-State Circuits Conference (ESSCIRC), and as a Guest Editor for the IEEE Journal of Solid-State Circuits in 2014. He has been a Distinguished Lecturer of IEEE.