Valtteri Karmitsa

System-on-chips (SoCs) are complex entities consisting of multiple hardware and software components. This complexity presents challenges in their design, verification, and validation. Traditional verification processes often test hardware models in isolation until late in the development cycle. As a result, cooperation between hardware and software development is also limited, slowing down bug detection and fixing.
This thesis aims to develop, implement, and evaluate a co-simulation-based pre-validation methodology to address these challenges. The approach allows for the early integration of hardware and software, serving as a natural intermediate step between traditional hardware model verification and full system validation. The co-simulation employs a QEMU CPU emulator linked to a register-transfer level (RTL) hardware model. This setup enables the execution of software components, such as device drivers, on the target instruction set architecture (ISA) alongside cycle-accurate RTL hardware models.
The thesis focuses on two primary applications of co-simulation. Firstly, it allows software unit tests to be run in conjunction with hardware models, facilitating early communication between device drivers, low-level software, and hardware components. Secondly, it offers an environment for using software in functional hardware verification.
A significant advantage of this approach is the early detection of integration errors. Software unit tests can be executed at the IP block level with actual hardware models, a task previously only possible with costly system-level prototypes. This enables earlier collaboration between software and hardware development teams and smoothens the transition to traditional system-level validation techniques.
Key words: co-simulation, QEMU, virtual platform.

Raju Ahamed

This thesis focuses on the design and characterization of millimeter-wave monolithic active and passive circuits for 5G-and-beyond 5G communication systems. Specifically, this thesis focuses on different active and passive components, the transmit-receive (T/R) switch, the low-noise amplifier (LNA), the power amplifier (PA), the bidirectional PALNA, the power detector, the phase shifter, and the receiver chain for mm-wave applications. This dissertation presents an overview of the research topic and summarizes the major outcomes of this thesis presented in six publications. Various issues and challenges associated with the design of mm-wave passive and active components in nanoscale BiCMOS technologies are described. Brief design details of different passive and active components have been presented. Among mm-wave passive components, different transmission lines including the microstrip line and coplanar waveguide are studied and modeled. The on-chip transformer and Marchand baluns are designed and utilized in different circuits. A wideband, low-loss and compact 3-dB differential quadrature generator is designed. The RF pads with the GSG configuration are designed with a compensation structure beneath the signal pad. The modeling techniques of the transistor operating in the high mm-wave region are presented. 

An E-band semi-switchless PALNA with a single-ended LNA and high-power differential PA is designed. The LNA and the PA are isolated from each other by the impedance matching networks and a differential switch. The semi-switchless PALNA achieves the lowest NF of 5.8 dB and the highest FOM in receive mode compared to the literature while it delivers a maximum power of +9.2 dBm at 76 GHz in the transmit mode. A compact and high-performance RF power detector is designed. It is demonstrated that the Meyer topology can be used to detect power at mm-wave frequencies with a suitable impedance matching network. The design of an E-band receiver frontend containing an LNA, a phase shifter, a buffer amplifier, and a switch at the input and the output for a phased array application is presented. The measured peak gain is 18.5 dB with a 3-dB bandwidth of 23 GHz from 56 to 79 GHz and the minimum noise figure is 9 dB at 75 GHz. A compact vector modulator phase shifter operating from 200 GHz to 250 GHz is designed utilizing a compact and differential I/Q generator. The achieved gain is -10.3 dB at 230 GHz with the maximum gain setting and the maximum rms gain and phase errors of 1.25 dB and 10° from 200 GHz to 250 GHz, respectively. A high-gain phase shifter chain is designed by adding an LNA to the input of the phase shifter and an additional gain amplifier at the output of the phase shifter. The measured peak gain from the phase shifter chain is 20 dB at 230 GHz and the minimum noise figure of 11.5 dB at 230 GHz. The high-gain phase shifter is capable of 360° phase tuning and 10 dB of gain tuning.