Increasing Role of Silicon Photonics and Criticality of Advanced Packaging Technologies to Meet Future Compute Demands

#photonics #heterogeneous #integration #2.5D #3D #advanced #packaging
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-- bandwidth needs, compute demands, energy, chiplets, photonics integration, systems ...


As the demand for high-performance computing continues to surge, driven largely by advances in artificial intelligence and other data-intensive applications, the semiconductor industry faces growing challenges in meeting these requirements. Traditional approaches, constrained by the slowing of Moore’s Law and the end of Dennard Scaling, are proving inadequate in addressing the exponential increase in compute and bandwidth needs. Silicon Photonics is emerging as a key technology to overcome these limitations. By leveraging the unique properties of silicon for optical communication, Silicon Photonics can offer significant improvements in data transmission speeds and energy efficiency compared to conventional electrical interconnects. This technology has the potential to reduce latency and power consumption, making it a compelling solution for next-generation data centers and high-performance computing systems.
Advanced Packaging Technologies are equally critical in this evolving landscape. As chips become more complex and power-hungry, innovative packaging solutions such as chiplets and advanced integration methods are essential to manage power consumption and thermal issues while enhancing performance. These technologies enable more efficient use of silicon area, improved thermal management, and higher bandwidth connections between components. In this talk, we will explore how Silicon Photonics and advanced packaging technologies are not just complementary but essential to addressing the challenges of future compute demands. We will discuss the current state of these technologies, their potential to transform the semiconductor industry, and the ongoing efforts to integrate them into scalable, high-performance systems.



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  • Date: 10 Oct 2024
  • Time: 12:00 PM to 01:00 PM
  • All times are (UTC-07:00) Pacific Time (US & Canada)
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  • Starts 06 September 2024 12:00 AM
  • Ends 10 October 2024 01:00 PM
  • All times are (UTC-07:00) Pacific Time (US & Canada)
  • No Admission Charge


  Speakers

Sandeep Sane of Lightmatter

Biography:

Sandeep Sane is the Senior Director and Head of Packaging at Lightmatter, where he leads the development and execution of packaging technologies for the Passage and Envise product lines. Before joining Lightmatter, Sandeep served as a Principal Engineer in the Assembly and Test Technology Division at Intel. He brings extensive expertise in Silicon-Package-System Architecture, focusing on integrated solutions that optimize silicon-package design, fabrication, assembly processes, reliability, and cost. Sandeep holds over 20 patents and is a co-inventor of Intel’s EMIB and Co-EMIB packaging technologies, which have been implemented across various Intel products. His contributions to the field include numerous technical articles published in conferences and journals, as well as a book chapter. He is an active member of ASME and engages in conference organization related to packaging technologies. Earlier in his career, he worked at IBM’s Micro-Electronics Division in Endicott, NY, as a Development Staff Engineer. He earned his M.S. and Ph.D. from Caltech in 2000 and his B.S. from IIT Bombay (Mumbai), India, in 1995.