IEEE SSCS Oregon Chapter October Meeting and Seminar (Hybrid)
IEEE SSCS Oregon Chapter October Meeting and Seminar
Join us for a talk from SSCS Distinguished Lecturer Prof. Makoto Nagata from Kobe University, Kobe, Japan, on Monday, October 21st, 2024. The seminar will be held from 11:00am to 12:00pm (PST) via a Hybrid format. Please register for the meeting link and information.
Topic:
Secure Packaging, Tamper Resistance, and Supply Chain Security of IC Chips
Abstract:
Semiconductor products are potentially compromised for theft, falsification or invalidation by adversarial attempts and even due to unexpected disturbances. This talk provides an overview of physical security threats among semiconductors, and then discusses a broad range of countermeasure techniques. Secure packing exploits vertical structures using post wafer process technologies such as through Si vias, Si backside membranes and Si interposers for proactive prevention from destructive or nondestructive intrusions. Tamper resistance is achieved at the IC level with analog techniques to protect digital functionality. Supply chain security uses hardware Trojan free design verification as well as authentication strategies. Silicon examples will be demonstrated.
Speaker Biography:
Makoto Nagata (Senior Member, IEEE) received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Hiroshima, Japan, in 2001. He was a Research Associate at Hiroshima University from 1994 to 2002, an Associate Professor at Kobe University, Kobe, Japan, from 2002 to 2009, where he was promoted to a Full Professor in 2009. His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, 2.5D and 3D system integration, as well as their applications for hardware security and hardware safety, and cryogenic electronics for quantum computing.
Dr. Nagata is a Senior Member of IEICE. He has been a member of a variety of technical program committees of international conferences, such as the Symposium on VLSI Circuits (2002–2009), Custom Integrated Circuits Conference (2007–2009), Asian Solid-State Circuits Conference (2005–2009), International Solid-State Circuits Conference (2014-2022), European Solid- State Circuits Conference (since 2020), and many others. He chaired the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-2022) and served for an Executive Committee Member (2023-present). He was the Technical Program Chair (2010–2011), the Symposium Chair (2012–2013), and an Executive Committee Member (2014–2015) for the Symposium on VLSI circuits. He was the IEEE Solid-State Circuits Society (SSCS) AdCom member (2020-2022), the distinguished lecturer (2020-2021, and 2024-present), and currently serves as the chapters vice chair (2022-) of the society. He is an associate editor for IEEE Transactions on VLSI Systems (since 2015).
Date and Time
Location
Hosts
Registration
- Date: 21 Oct 2024
- Time: 11:00 AM to 12:00 PM
- All times are (GMT-08:00) US/Pacific
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- 2111 NE 25th Ave
- Hillsboro, Oregon
- United States 97124
- Building: Jones Farm Conference Center
- Room Number: JFCC-119
- Starts 01 October 2024 12:00 PM
- Ends 21 October 2024 08:00 AM
- All times are (GMT-08:00) US/Pacific
- No Admission Charge
Speakers
Prof. Makoto Nagata of Kobe University
Secure Packaging, Tamper Resistance, and Supply Chain Security of IC Chips
Semiconductor products are potentially compromised for theft, falsification or invalidation by adversarial attempts and even due to unexpected disturbances. This talk provides an overview of physical security threats among semiconductors, and then discusses a broad range of countermeasure techniques. Secure packing exploits vertical structures using post wafer process technologies such as through Si vias, Si backside membranes and Si interposers for proactive prevention from destructive or nondestructive intrusions. Tamper resistance is achieved at the IC level with analog techniques to protect digital functionality. Supply chain security uses hardware Trojan free design verification as well as authentication strategies. Silicon examples will be demonstrated.
Biography:
Makoto Nagata (Senior Member, IEEE) received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Hiroshima, Japan, in 2001. He was a Research Associate at Hiroshima University from 1994 to 2002, an Associate Professor at Kobe University, Kobe, Japan, from 2002 to 2009, where he was promoted to a Full Professor in 2009. His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, 2.5D and 3D system integration, as well as their applications for hardware security and hardware safety, and cryogenic electronics for quantum computing.
Dr. Nagata is a Senior Member of IEICE. He has been a member of a variety of technical program committees of international conferences, such as the Symposium on VLSI Circuits (2002–2009), Custom Integrated Circuits Conference (2007–2009), Asian Solid-State Circuits Conference (2005–2009), International Solid-State Circuits Conference (2014-2022), European Solid- State Circuits Conference (since 2020), and many others. He chaired the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-2022) and served for an Executive Committee Member (2023-present). He was the Technical Program Chair (2010–2011), the Symposium Chair (2012–2013), and an Executive Committee Member (2014–2015) for the Symposium on VLSI circuits. He was the IEEE Solid-State Circuits Society (SSCS) AdCom member (2020-2022), the distinguished lecturer (2020-2021, and 2024-present), and currently serves as the chapters vice chair (2022-) of the society. He is an associate editor for IEEE Transactions on VLSI Systems (since 2015).
Agenda
11:00am - 12:00pm: Professional/Career Seminar