Advanced semiconductor packaging and the need for a workforce to support the growing semiconductor industry in the USA

#Chips-Act #semiconductors #advanced-packaging #reshoring #workforce
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IEEE Oregon EPS/CASS Joint Chapter

 

Advanced semiconductor packaging and the need for a workforce to support the growing semiconductor industry in the USA

with Chris Bailey, Director, Advanced Semiconductor Packaging Centre, Arizona State University

Date/Time: November 22nd, 2024 @3:30-5:00 PM PT

Location: PCC Willow Creek Center, Room 313

(the seminar room sponsored by the PSU ECE department)

241 SW Edgeway Drive (near SW 185th and Baseline Road)

Beaverton, OR 97006

Directions: http://www.pcc.edu/about/locations/willow-creek/

 

Due to the Chips Act (USA), significant investments and initiatives are taking place across the US to support reshoring and nearshoring electronics packaging capabilities. For example, at Arizona State University (ASU) we are installing a 300mm fan out wafer level packaging pilot line as a core platform for advanced semiconductor packaging and heterogeneous integration. In addition to research and development activities, workforce development is a critical activity in supporting our electronics packaging industries. At ASU, we are developing and promoting stackable micro-credentials in advanced semiconductor packaging.

This presentation will discuss developments and opportunities in advanced semiconductor packaging, the opportunities for students in the growing semiconductor workforce here in the US, and opportunities for universities and industry to collaborate in this exciting area of technology.

 


  Date and Time

  Location

  Hosts

  Registration


  • Date: 22 Nov 2024
  • Time: 03:30 PM to 05:00 PM
  • All times are (UTC-08:00) Pacific Time (US & Canada)
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  • PCC Willow Creek Center
  • 241 SW Edgeway Drive
  • Beaverton, Oregon
  • United States 97006
  • Room Number: 311
  • Contact Event Host
  • Co-sponsored by Portland State University ECE Department
  • Starts 14 November 2024 12:00 AM
  • Ends 22 November 2024 12:00 AM
  • All times are (UTC-08:00) Pacific Time (US & Canada)
  • No Admission Charge

  Speakers

Chris Bailey of Arizona State University

Topic:

Advanced semiconductor packaging and the need for a workforce to support the growing semiconductor industry in the USA

Advanced semiconductor packaging is now used by semiconductors companies to meet the requirements (e.g. bandwidth, latency, power, etc) for AI and HPC applications using heterogeneous multi-chiplet architectures. These packaging techniques include flip-chip, wafer-level packaging (both fan-in and fan-out) and 3D-Heterogeneous Integration (3D-HI) and are supported by advancements in EDA/Modelling and materials characterization to address the challenges posed by the ending of Moore’s Law.

Due to the Chips Act (USA), significant investments and initiatives are taking place across the US to support reshoring and nearshoring electronics packaging capabilities. For example, at Arizona State University (ASU) we are installing a 300mm fan out wafer level packaging pilot line as a core platform for advanced semiconductor packaging and heterogeneous integration. In addition to research and development activities, workforce development is a critical activity in supporting our electronics packaging industries. At ASU, we are developing and promoting stackable micro-credentials in advanced semiconductor packaging.

This presentation will discuss developments and opportunities in advanced semiconductor packaging, the opportunities for students in the growing semiconductor workforce here in the US, and opportunities for universities and industry to collaborate in this exciting area of technology.

 

Biography:

Chris Bailey joined Arizona State University in 2022. He is Director of the Advanced Semiconductor Packaging Centre and Professor in Electronics Packaging and Reliability. Before joining ASU, he was Associated Dean for Research at the University of Greenwich, UK. He has published 400+ archival papers, and from 2020-2021 was the President of the IEEE Electronics Packaging Society. He also serves on the Heterogeneous Integration Roadmap as chapter co-chair for the Co-Design and Modelling and Simulation Chapters.

 

Email:

Address:Advanced Semiconductor Packaging Centre , Arizona State University , Tempe, United States