Dr. Bowman

Abstract:

System-on-chip (SoC) processors across a wide range of market segments, including Internet of Things (IoT), mobile, laptop, automotive, and datacenter, experience dynamic device, circuit, and system parameter variations during the operational lifetime.  These dynamic parameter variations, including supply voltage droops, temperature changes, transistor aging, and workload fluctuations, degrade processor performance, energy efficiency, yield, and reliability.  This lecture introduces the primary variation sources and the negative impact of these variations across voltage and clock frequency operating conditions.  Then, this lecture presents adaptive processor designs to mitigate the adverse effects from dynamic parameter variations while highlighting the key trade-offs and considerations for product deployment.

Biography:

Keith A. Bowman is a Principal Engineer and Director of the System-on-Chip (SoC) Research Lab at Qualcomm Technologies, Inc. in Raleigh, NC, USA.  He directs the research and development of circuit and system technologies to improve the performance, energy efficiency, yield, reliability, and security of Qualcomm processors.  He pioneered the invention, design, and test of Qualcomm’s first commercially successful circuit for mitigating the adverse effects of supply voltage droops on processor performance, energy efficiency, and yield.  He received the B.S. degree from North Carolina State University in 1994 and the M.S. and Ph.D. degrees from the Georgia Institute of Technology in 1995 and 2001, respectively, all in electrical engineering.  From 2001 to 2013, he worked in the Technology Computer-Aided Design (CAD) Group and the Circuit Research Lab at Intel Corporation in Hillsboro, OR, USA.  In 2013, he joined Qualcomm.

Dr. Bowman has published 90+ technical papers in refereed conferences and journals, authored one book chapter, received 35+ US patents and 60+ international patents, and given 50+ tutorial, special session, and keynote presentations.  He received the 2016 Qualcomm Corporate Research and Development (CRD) Distinguished Contributor Award for Technical Contributions, representing CRD’s highest recognition, for the pioneering invention of the auto-calibrating adaptive clock distribution circuit, which significantly enhances processor performance, energy efficiency, and yield and is integral to the success of the Qualcomm® Snapdragon™ 820 and future processors.  He received the 2022 Qualcomm IP Achievement Award for high-quality inventions, leading to strong processor performance and energy-efficiency improvements and differentiated products.  Since 2018, he served on the Qualcomm Low-Power Circuit Design Patent Review Board.  In 2019 and 2020, he was as an IEEE SSCS Distinguished Lecturer (DL).  He is currently serving a 2nd 2-year term as an IEEE SSCS DL.  From 2020 to 2023, he served as an IEEE SSCS Mentor.  He was the International Technical Program Committee (ITPC) Chair and the General Conference Chair for ISQED in 2012 and 2013, respectively, and for ICICDT in 2014 and 2015, respectively.  He served on the ISSCC ITPC as a member of the Digital Circuits (DCT) Subcommittee from 2016 to 2020, as the DCT Chair from 2020 to 2024, and as the Program Vice Chair in 2025.  He currently serves as the ISSCC 2026 Program Chair.  He is a Fellow of the IEEE.

Dr. Loke

Abstract:

Despite the much debated end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for three years and 2nm gate-all-around SoCs anticipated late this year. Area scaling extensively driven by design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the transition to the gate-all-around device architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated.

Biography:

Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel’s gate-all-around CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. Alvin received a BASc from the University of British Columbia, and MS and PhD from Stanford. After several years in CMOS process integration, he has since worked on analog/mixed-signal design focusing on a variety of wireline links including chiplet IOs, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary and SSCS Global Chapters Chair. Alvin frequently speaks on CMOS technology and its impact on analog design, having authored invited publications including the CICC 2018 Best Paper and short courses at ISSCC, VLSI Symposium, CICC, and BCICTS.

Dr. Tokunaga

Abstract:

Next-generation SoCs for the Zetta-Scale computing era will be developed with increased integration of our compute, memory and communication systems in optimized advanced packaging solutions. The complexity of these systems is growing exponentially and the need to increase reliability while achieving high energy-efficiency is paramount. We will explore the challenges and opportunities in technology and circuits to enable resilient, reliable and secure circuits and systems.

Biography:

Carlos Tokunaga is a Principal Engineer at Intel Corporation and leads the Reliability and Resiliency Circuit Technology Group at the Circuit Research Lab. Carlos received the B.S. degree in electronics engineering from the University of Los Andes, Bogotá, Colombia, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2005 and 2008, respectively. He is an IEEE Senior Member and serves as a Member-at-Large in the IEEE SSCS Adcom. He currently serves as the TPC Chair for CICC and is a TPC member of ISSCC. He served in the VLSI Symposium TPC 2019-2024. He serves as an Associate Editor for the Open Journal of SSCS and is an SSCS Distinguished Lecturer 2025-2026. He received Intel Lab’s Gordon Moore Award in 2018. He has published over 50 technical papers in refereed conferences and journals and received 78 patents.