Webinar: Drivers and realms of distributed AI computing with More Moore

#More #Moore #AI #computing #Logic #and #Memory #technologies #Communication #IRDS #Roadmap
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Distributed AI computing is augmenting the human productivity to new horizons and enhancing the natural interfaces between human and computer. More Moore compute, memory technologies, and scale-up/scale-out communication fabric are key ingredients for the scalability of distributed AI computing. In this webinar IRDS More Moore roadmap and its readiness for high volume manufacturing will be presented with those ingredients enabling scalability of such systems under the scarce constraints of power, thermal, and shoreline/footprint performance in a horizon of next 15 years.



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  • Co-sponsored by SiNANO, INPACE, IRDS
  • Starts 13 November 2025 11:00 PM UTC
  • Ends 24 November 2025 11:00 PM UTC
  • No Admission Charge


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Mustafa Badaroglu of Qualcomm

Topic:

Drivers and realms of distributed AI computing with More Moore

Distributed AI computing is augmenting the human productivity to new horizons and enhancing the natural interfaces between human and computer. More Moore compute, memory technologies, and scale-up/scale-out communication fabric are key ingredients for the scalability of distributed AI computing. In this webinar IRDS More Moore roadmap and its readiness for high volume manufacturing will be presented with those ingredients enabling scalability of such systems under the scarce constraints of power, thermal, and shoreline/footprint performance in a horizon of next 15 years.

Biography:

Mustafa Badaroglu is Director of Engineering at Qualcomm for AI chipset/system development with focus on system-technology-co-optimization (STCO), custom memory for data center, mobile, compute, and XR products. Across more than 30 years of industry experience he had various assignments for the design and management of mobile, compute, graphics, and automotive chipsets from concept to volume production, deployment of AI platforms for automotive and smart manufacturing, process technology selection/ramping, analog and digital design automation, and STCO/DTCO. He holds more than one hundred published patents, and (co)-authored over one hundred publications in scientific journals/proceedings. He is a workstream member of American Semiconductor Innovation Coalition (ASIC), Si2 alliance, DRAM JEDEC, and IEEE IRDS More Moore global chair. He holds PhD in Electrical Engineering and Master in Industrial Management, both from the Catholic University of Leuven.