Enabling Advanced Transceiver Verification for Chiplet Architectures
Enabling Advanced Transceiver Verification
The continued demand for higher data rates in modern electronics has driven the evolution of high-speed transceivers, particularly within complex multi-die and chiplet architectures. These advanced packaging schemes, including 3D IC integration and chip-to-chip/chip-to-interposer configurations, introduce unprecedented signal integrity challenges due to inter-symbol interference, channel loss, dispersion and parasitic coupling effects. Accurate verification of these intricate high-speed links necessitates a sophisticated approach that can account for both the non-linear behavior of custom-designed transceivers including channel paths (requiring SPICE-level analysis) and the algorithmic equalization schemes (like CTLE and DFE) typically described by IBIS-AMI models. Traditional verification flows often struggle to seamlessly integrate these diverse modeling paradigms, leading to fragmented analysis and increased design iterations. This presentation highlights a unified simulation methodology that combines SPICE-level circuit simulation with IBIS-AMI modeling for comprehensive transceiver verification in multi-die and chiplet applications. The approach enables designers to precisely analyze custom transceiver IP while simultaneously integrating vendor-provided IBIS-AMI models for external chiplets, ensuring accurate representation of the entire high-speed link. The methodology supports essential elements such as S-parameter models, lossy coupled transmission lines, and DSPF from parasitic extractions, all critical for modeling the physical realities of multi-die environments. The integrated approach, demonstrated with examples using Siemens EDA's Solido Simulation Suite and HyperLynx tools, provides consistent, accurate analysis from circuit-level transceivers up to system-level interconnects, significantly streamlining verification and accelerating time-to-market for next-generation chiplet-based designs.
Date and Time
Location
Hosts
Registration
-
Add Event to Calendar
- 5001 Great America Parkway
- Santa Clara, California
- United States 95054
- Contact Event Hosts
- Co-sponsored by Siemens EDA
Speakers
Dr. Scott Wedge of Siemens EDA
Enabling Advanced Transceiver Verification
Biography:
Scott Wedge is an experienced R&D leader in the electronics, semiconductor, and EDA industries with a history of creating innovative modeling, simulation, and verification solutions for the design of next-generation circuits and systems. His team at Siemens EDA develops AMS/RF simulation algorithms, S-parameter modeling approaches, and new methods for high-gigabit signal integrity analysis. Scott’s experience includes IC and PCB design with a variety of semiconductor and substrate technologies that include high-performance analog, mixed-signal, RF/uW/mmW and MEMS functionality. He is a licensed Professional Engineer, experienced Principal Investigator, and active member of the IEEE. He holds a PhD in Electrical Engineering from Caltech.
Enabling Advanced Transceiver Verification