Gilson of UFRGS

Charge capture and emission by defects (traps) close to the Dielectric-Semiconductor interface is a major source of noise in modern MOS devices. It also causes Bias Temperature Instability (BTI). A comprehensive physics-based modeling and simulation approach for BTI, RTN and low-frequency noise is reviewed, discussed and summarized. It allows for the derivation of analytical formulations for 1/f noise (frequency domain), RTN (time domain) and BTI (aging) using a single modeling framework, where model parameters are the same in frequency and time domain. Noise and BTI levels can vary by several orders of magnitude in deeply scaled devices, making variability a major concern in advanced MOS technologies. To ensure proper circuit design in this scenario, it is necessary to identify the fundamental mechanisms responsible for variability in noise and BTI. Time domain analysis is relevant for the analysis of digital and mixed-signal circuits. In digital circuits, the RTN chronological statistics, especially trap occupancy switching, have direct impacts on circuit performance and reliability, as degradations like jitter of signals happen when a trap switches state. The area scaling of RTN induced jitter (phase noise) and its variability is detailed and discussed, aiming to support circuit designers in transistor sizing towards a more reliable design. The applicability of the model here presented to the evaluation of logic gates and circuits is also discussed.

Biography:

Gilson Wirth is currently a Full Professor at the Electrical Engineering Department at the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. He received the BSEE and MSc degrees from UFRGS in 1990 and 1994 respectively. In 1999, he received the Dr.-Ing. EE degree from TU Dortmund. His research work focuses on modeling and electrical simulation of charge trapping in the context of Bias Temperature Instability (BTI), Low-Frequency Noise (1/f and RTN) and Hot Carrier Degradation (HCD). He has also worked on ionizing radiation effects (TID and SET/SEU) on semiconductor devices. He is currently a Distinguished Lecturer of the IEEE Electron Devices Society. He also was a Distinguished Lecturer of the IEEE Circuits and Systems Society (2010-2011). A list of publications may be found at https://www.scopus.com/authid/detail.uri?authorId=8700162500.

Address:United States

Xinfei of SJTU

The shift-left paradigm in Electronic Design Automation (EDA) seeks to move physically aware analysis into earlier design stages to improve quality, reduce iteration cost, and enable predictive digital twins. A key challenge is determining where early prediction is both accurate and impactful. This lecture presents AI-fused shift-left methodologies across critical stages of the EDA flow, from pre-RTL design to signoff, covering both digital and analog circuits. Examples include physically aware timing models integrated into logic synthesis, macro connectivity–aware optimization for improved routability, fast timing estimation tightly coupled with ECO processes for accelerated closure, and large language model–assisted analog circuit sizing. The lecture concludes with opportunities and challenges in accuracy, generalization, and toolchain integration, offering practical insights into how AI-enabled prediction can reshape modern design automation workflows.

Biography:

Xinfei Guo is an Associate Professor at Shanghai Jiao Tong University (SJTU), where he leads the Intelligent Circuits, Architectures, and Systems (iCAS) Laboratory. He received his PhD from the University of Virginia and MS from the University of Florida. Prior to joining academia, he worked at NVIDIA and IBM Research in the US. His research focuses on software–hardware co-design for efficient AI systems, AI-driven EDA, and reliable computing architectures. His work has resulted in over 70 publications and three books, and has been recognized with multiple best paper and best presentation awards. Dr. Guo currently serves as Associate Editor-in-Chief of IEEE Transactions on VLSI Systems (TVLSI) and as an Associate Editor for Integration, the VLSI Journal. He is actively involved in the research community, serving as General Co-Chair of IEEE MCSoC 2026, Publication Chair of AICAS 2026, and TPC Co-Chair of ISICAS 2025, and regularly contributes to major conferences including DAC, CICC, ICCAD, and ISCAS. He has been selected as a Distinguished Lecturer of the IEEE Circuits and Systems Society for 2026–2027, and is a Senior Member of IEEE and ACM.

Address:United States

Yongfu of Shanghai Jiao Tong University, China

In the realm of circuit logic and machine learning models (LLMs), the availability and quality of datasets play a pivotal role in advancing research and development. This talk explores the critical importance of datasets in driving circuit LLM, focusing on a diverse array of datasets ranging from academic papers to commercial device specifications and physical designs. We delve into specific techniques, such as converting images to netlists, web crawling for extracting paper content, and computer vision for extracting data from figures. By leveraging these datasets and techniques, we enhance the accuracy, efficiency, and applicability of LLM in circuit design and analysis.

Biography:

Yongfu Li received the BEng and PhD degrees from the National University of Singapore. He is currently an Associate Professor (tenured) at Shanghai Jiao Tong University, China. His research interests include analog/mixed signal circuits, biomedical signal processing, and circuit automation. He is an active IEEE volunteer, where he served as Vice-President (2026-2027), Board of Governors (BoG), and R10 Member At Large (2023-2025, 2020-2021) of the IEEE Circuits and Systems Society, an AdCom Member of the IEEE Biometrics Council, a member of the IEEE DataPort Steering Committee, Chair of the IEEE Data Competition Committee, Chair of the IEEE CASS Standard Activities Sub Division, and the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Steering Committee. Throughout his career, he has earned numerous academic, industrial, and IEEE awards, including the IEEE MGA Larry K. Wilson Transnational Award (2025), IEEE EAB Society/Council Professional Development Award (2023), IEEE MGA YP Achievement Award (2022), and IEEE YP Hall of Fame Award (2021).