seminar on Template based high-level and logic synthesis with approximate computation for higher and energy efficient computing
Although FPGA or hardware-based implementation of software can give us not only higher performance but also energy efficient computing, efficient implementation algorithms as hardware and as software can be significantly different. Typical high-level synthesis methods may not concentrate on this issue, as they are targeting general hardware designs. In this talk performance directed synthesis targeting throughput based computations rather than transitional high-level synthesis techniques is proposed based on template-based approaches. With templates, given data flow graphs are automatically converted into the ones for high performance with FPGA implementation by using SAT-based automatic refinement methods. Then we further explore the use of approximate computation to reduce the amount of hardware while keeping the required accuracy. We discuss the proposed techniques from the viewpoints of a couple of case studies, such as neural network simulation and HEVC (High Efficiency Video Coding)
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- Start time: 07 Aug 2017 10:00 AM
- End time: 08 Aug 2017 11:30 AM
- All times are (UTC+08:00) Hong Kong
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- G6315, Green Zone, AC1
- DEPARTMENT OF ELECTRONIC ENGINEERING
- Hong Kong, Guangdong
- China
- Building: City University of Hong Kong
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- Co-sponsored by City University of Hong Kong
Speakers
Prof. Masahiro Fujita of VLSI Design and Education Center, University of Tokyo
Template based high-level and logic synthesis with approximate computation for higher and energy efficient computing
Biography:
Masahiro Fujita received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools, including enhancements of BDD/SAT-based techniques. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group developing a formal verifier for real-life designs having more than several million gates. The developed tool has been used in production internally at Fujitsu and externally as well. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has done innovative work in the areas of hardware verification, synthesis, testing, and software verification—mostly targeting embedded software and web-based programs. He has been involved in a Japanese governmental research project for dependable system designs and has developed a formal verifier for C programs that could be used for both hardware and embedded software designs. The tool is now under evaluation jointly with industry under governmental support. He has authored and co-authored 10 books, and has more than 200 publications. He has been involved as program and steering committee member in many prestigious conferences on CAD, VLSI designs, software engineering, and more. His current research interests include synthesis and verification in SoC (System on Chip), hardware/software co-designs targeting embedded systems, digital/analog co-designs, and formal analysis, verification, and synthesis of web-based programs and embedded programs.
Enquiry: Dr. Ray C.C. Cheung, Department of Electronic Engineering, CityU
Tel: 3442 9849, Fax:3442 0562