Workshop on Fast Design of Digital Systems
This two-day workshop is aimed at researchers and hardware engineers. It covers fast design of digital systems (e.g. FPGA, ASIC) with the electronic design tool AHIR. AHIR enables the hardware compilation of a circuit description. The input entry is a high‐level programming language and the output is fully functional VHDL. There will be both theory (day 1) and lab (day 2) sessions.
Date and Time
- Start time: 08 Mar 2018 08:30 AM
- End time: 09 Mar 2018 12:30 PM
- All times are Europe/Madrid
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- Universidad CEU San Pablo
- Campus de Montepríncipe
- Alcorcon, Madrid
- Spain 28925
- Building: Escuela Politécnica Superior
- Co-sponsored by Universidad CEU San Pablo
Madhav P. Desai of Indian Institute of Technology
Madhav P. Desai holds a degree in Electrical Engineering from IIT Bombay
and a PhD degree from University of Illinois in Urbana‐Champaign. During
the period 1992‐1996 he was with the Semiconductor Engineering Group of
Digital Equipment Corporation in Hudson, MA, where he worked as
Principal Engineer developing two of the fastest CMOS microprocessors in
history. Currently, he is a Full Professor at the Department of Electrical
Engineering, Indian Institute of Technology, Bombay. His research lines
cover VLSI design, circuits and systems, and combinatorial algorithms.
8 March. 8:30h‐12:30h. Introduction to the AHIR tool suite.
- Language Aa
- VHDL generation
9 March. 8:30h‐12:30h. Case study: real‐time ECG characterization.