Affordable Digital Beamforming for 5G Wireless

#CMOS #5G #communications
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The next generation wireless networks – 5G- promises wider bandwidth to enable wide range of applications including autonomous vehicle, virtual reality and internet of things. A key feature in these receivers is beamforming that compensates for pathloss and allows directional communication. Although digital beamforming is the holy grail in the antenna array technology, high resolution ADCs are not affordable in each receiver path at this speed. A more pragmatic approach is hybrid beamforming that combines RF and LO and digital where appropriate. First, cascaded PLL based LO beamforming is introduced that achieves lower phase noise and eliminate the high frequency clock distribution power.  The cascaded PLL consumes 26.9-mW from a 1-V supply and achieves less than 100-fs integrated jitter with -116.2 dBc/Hz and -112.6 dBc/Hz phase noise at 1-MHz offset for the integer-N and the fractional-N modes, respectively. The fractional-N single-stage and cascaded PLLs achieve figure-of-merits (FoM) of -230.58 dB and -248.75 dB, respectively. The FoM of the proposed cascaded PLL outperforms that of the reported state-of-the-art mm-Wave synthesizers making it a suitable candidate for 5G transceivers. The digital beamforming takes advantage of the channel diversity by distributing the resolution according to channel SNR. In addition, it utilizes the correlated information between channels to perform energy efficient digitization of received signals. The collaborative ADC is designed with 8 SAR units each having 6-bit of resolution and 2-bit Flash to monitor SNR. With the help of a coarse 2-bit flash, the ADC can detect change in channel SNR, and accordingly reconfigure the four ADCs with variable resolution from 6-bit to 11-bit with less than 1 ns mode switching time. This collaborative ADC performance is compared with all 11- and all 9-bit. It reduces area and power by half and 41% respectively with only 10% degradation of overall SNDR.



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  • 19 Union St.
  • Kingston, Ontario
  • Canada
  • Building: Walter LIght Hall
  • Room Number: 302

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Masum Hossain

Topic:

Affordable Digital Beamforming for 5G Wireless

The next generation wireless networks – 5G- promises wider bandwidth to enable wide range of applications including autonomous vehicle, virtual reality and internet of things. A key feature in these receivers is beamforming that compensates for pathloss and allows directional communication. Although digital beamforming is the holy grail in the antenna array technology, high resolution ADCs are not affordable in each receiver path at this speed. A more pragmatic approach is hybrid beamforming that combines RF and LO and digital where appropriate. First, cascaded PLL based LO beamforming is introduced that achieves lower phase noise and eliminate the high frequency clock distribution power.  The cascaded PLL consumes 26.9-mW from a 1-V supply and achieves less than 100-fs integrated jitter with -116.2 dBc/Hz and -112.6 dBc/Hz phase noise at 1-MHz offset for the integer-N and the fractional-N modes, respectively. The fractional-N single-stage and cascaded PLLs achieve figure-of-merits (FoM) of -230.58 dB and -248.75 dB, respectively. The FoM of the proposed cascaded PLL outperforms that of the reported state-of-the-art mm-Wave synthesizers making it a suitable candidate for 5G transceivers. The digital beamforming takes advantage of the channel diversity by distributing the resolution according to channel SNR. In addition, it utilizes the correlated information between channels to perform energy efficient digitization of received signals. The collaborative ADC is designed with 8 SAR units each having 6-bit of resolution and 2-bit Flash to monitor SNR. With the help of a coarse 2-bit flash, the ADC can detect change in channel SNR, and accordingly reconfigure the four ADCs with variable resolution from 6-bit to 11-bit with less than 1 ns mode switching time. This collaborative ADC performance is compared with all 11- and all 9-bit. It reduces area and power by half and 41% respectively with only 10% degradation of overall SNDR.

Biography:

Dr. Masum Hossain completed his Ph.D. at the University of Toronto in 2010. Prior to that, received his B.Sc. Degree from the Bangladesh University of Engineering and Technology, and M.Sc. degree from Queen’s University, in 2002 and 2005, respectively. He joined the faculty of the University of Alberta Department of Electrical and Computer Engineering in 2013. Masum has spent several years in industrial research before returning to academia. He was with Intel Circuit Research Lab (CRL) as a graduate intern for 6 months. From 2008 to 2010, He was with Gennum Corp. in the Analog and Mixed Signal division and following that, he joined Rambus Lab as a senior member of technical staff. At Rambus, his research focused on advanced equalization and clock recovery techniques for high-speed interfaces. Masum won the best student paper award at the 2008 IEEE Custom Integrated Circuits (CICC) Conference. He also won Analog Device’s outstanding student designer award in 2010.

Address:University of Alberta, , Edmonton, Ontario, Canada