LECTURE ON TDCs FOR ADPLL (ALL-DIGITAL PLL) BY PROF. BOGDAN STASZEWSKI

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The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock
versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using ”free” but powerful digital logic.

This lecture covers topics related to the Time-to-Digital Converter design.



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  • Date: 20 Dec 2018
  • Time: 03:30 PM to 06:00 PM
  • All times are Poland
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  • AGH University of Science and Technology
  • Av. Mickiewicza 30
  • Cracow, Malopolskie
  • Poland 30-059
  • Building: B1
  • Room Number: 121