2nd Workshop on Fast Design of Digital Systems

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The Workshop on Fast Design of Digital Systems is a two-day event aimed at researchers and hardware engineers and covers the fast design of digital systems (e.g. FPGA, ASIC) with the electronic design tool AHIR. AHIR enables the hardware compilation of a circuit description. The input entry is a high-level programming language and the output is fully functional VHDL. All sessions are composed of theory and practice. Examples will be tested on FPGA boards. In day 1 there will be an overview on the latest FPGA trends provided by AVNET-Silica Engineers. This is the second edition of the Workshop, the first one took place in 2018.



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  • Start time: 20 Feb 2019 10:00 AM
  • End time: 21 Feb 2019 01:30 PM
  • All times are Europe/Madrid
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  • Universidad San Pablo CEU
  • Campus de Montepríncipe
  • Alcorcon, Madrid
  • Spain 28668
  • Building: Escuela Politécnica Superior
  • Co-sponsored by Universidad CEU San Pablo






Agenda

20 February

10:00-10:15 h: Welcome message (Gabriel Caffarena, USP-CEU)

10:15-11:00 h: New trends in FPGA and configurable Soc design (Ricardo Gómez Galarza, AVNET-Silica)

11:00-11:15 h: Coffee break

11:15-13:30h: Lab session I: Introduction to AHIR toolchain (Madhav P. Desai, IIT-Bombay)

 

21 February

 9:30-11:00h: Lab session II: More on AHIR toolchain  (Madhav P. Desai, IIT-Bombay)

 11:00-11:15h: Coffee break

 11:15-13:30h: Lab session III: Signal processing case study (Madhav P. Desai, IIT-Bombay)