“Two-day Workshop in VLSI Design with hands-on sessions using Cadence Tools” in collaboration with IEEE CAS Student chapter-GCET
Workshop covers topics in detail about
-> Brushing up Digital Design Basics (Combinational and Sequential), RTL Design (Industry Oriented Design Styles and Coding), Verification, Synthesis Flow, Design for test Flow.
Workshop Topics
Introduction to VLSI Design (ASIC Design Flow and FPGA Design Flow)
ASIC Design Flow (Design For Verification, Design For Synthesis, Design For Test, Physical Design).
RTL Design Using Verilog HDL
State Machine Coding
Writing Effective Testbenches Using Verilog
Gate Level Simulations
Basics Of Static Timing Analysis
Introduction to System Verilog
Assertion Based Verification (ABV)
Verification Methodologies (OVM/UVM)
Code Coverage and Functional Coverage
Applications of VLSI Technology in Artificial Intelligence, IOT etc.
Career Opportunities in VLSI and Scope of Projects.
Day1: ASIC Design Flow ,RTL Design Using Verilog HDL, State Machine Coding and Writing Logic and Effective Testbenches Using Verilog were covered with numerous example problems.
Day 2: Gate Level Simulations, Basics Of Static Timing Analysis & Career Opportunities in VLSI and Scope of Projects.Mr.Abhay Joshi,Development chair,Hyderabad Section, was invited to interact with our students on 23rd Feb, 2019 between 11:30AM to 12:30PM on IEEE membership drive, also shared his industry experience on wireless software development in relation to its interface with hardware or HW/SW co design/co-verification etc.
Date and Time
Location
Hosts
Registration
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Add Event to Calendar
- Geethanjali college of engineering and technology
- cheeryal(V), Keesara (M), Medchal district
- Hyderabad, Andhra Pradesh
- India 501301
- Building: I
- Room Number: vlsi lab
- Contact Event Host
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Prof. O V P R Siva Kumar
Advisor, IEEE CAS GCET SB Chapter
ogirala.sivakumar@gmail.com
- Co-sponsored by IEEE GCET - SB
- Starts 17 February 2019 03:30 AM UTC
- Ends 20 February 2019 09:30 PM UTC
- No Admission Charge
Speakers
Avinash Yadlapati of Mirafra Technologies
ASIC Design Flow ,RTL Design Using Verilog HDL, State Machine Coding and Writing Logic and Effective Testbenches
VLSI design, the methodology makes extensive use of CAD techniques, including multilevel simulation for all tasks associated with design simulation and layout. The methodology is intended to totally verify the system during the design phase, prior to the release of VLSI components for fabrication. Today many companies like Texas Instruments, Infineon, Alliance Semiconductors, Cadence, Synopsys, Celox Networks, Cisco, Micron Tech, National Semi-conductors, ST Microelectronics, Qualcomm, Lucent, Mentor Graphics, Analog Devices, Intel, Philips, Motorola and many other firms have been established and are dedicated to the various fields in "VLSI" like Programmable Logic Devices, Hardware Descriptive Languages, Design tools, Embedded Systems etc
Session Details:
Day1: ASIC Design Flow ,RTL Design Using Verilog HDL, State Machine Coding and Writing Logic and Effective Testbenches Using Verilog were covered with numerous example problems.
Day 2: Gate Level Simulations, Basics Of Static Timing Analysis & Career Opportunities in VLSI and Scope of Projects.
Biography:
Avinash Yadlapati, with 15 years of experience in ASIC Design, Verification and Implementation (Synthesis & Timing Closure). He worked extensively on Industry standard tools like Synopsys VCS, VCSMX, Cadence NCSIM, Mentor Tools, Synopsys Design Compiler, Synopsys Prime Time and IBM Einstimer. He has 10 years of experience in the ASIC Front End activities like RTL Coding, Verification, Synthesis and LEC and close to 4 years experience in Static Timing Analysis primarily on IBM Tools and Methodologies. Completed M.Tech (VLSI) From KL University, Vijayawada, AP and have also been trained initially at Bit Mapper Integration Technologies, Pune in ASIC Front End Methodologies. Have varied experience working at different customer sites in US, Europe, Korea, China and Singapore. I have also been instrumental in building teams and managing teams in different locations.
Email:
Address:Mirafra software Technologies Pvt. Ltd, 8-2-596 A&B, Road no-10,Banjarahills, Hyderabad, Andhra Pradesh, India, 500034
Abhay Joshi of IEEE Hyderabad Section
Benefits of IEEE Membership
Mr.Abhay Joshi was invited to interact with our students on 23rd Feb, 2019 between 11:30AM to 12:30PM on IEEE membership drive, also shared his industry experience on wireless software development in relation to its interface with hardware or HW/SW co design/co-verification etc.
Biography:
Mr. Abhay Joshi obtained his Bachelor of Engineering in Electronics and Communication from Osmania University, Hyderabad. He is the winner of IET scholarship with gold medal for the year 2015. He has undergone internship in IISc, Bangalore and IIT Delhi in 2016.
He is an active IEEE volunteer from the past 5 years, serving the IEEE Hyderabad Section in various roles such as Section Student Representative (SSR), Member of Young Professional Affinity Group. He currently serves as the Chair, Membership Development Committee for the IEEE Hyderabad Section as well as the Treasurer for IEEE Young Professionals - Hyderabad Section.
Email:
Address:644-645,6th floor, Al-Karim Trade Centre,Ranigunj, Secunderabad, Andhra Pradesh, India, 500003
Agenda
The aim of this workshop is to provide hands-on experience on the state-of-the-art Cadence EDA tools for VLSI Design. The participants will be able to do mini and major projects and shall subsequently open-up career opportunities for them in Core Electronics. To get familiarity with the different phases of the ASIC Design Flow