Superconducting Electronics for Quantum Computing
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The potential of quantum computing to achieve exponential improvements in computational power can only be realized by manufacturable circuit design and fabrication processes. The two talks at this event describe recent advances in superconducting CPU and memory elements necessary for a Reciprocal Quantum Logic (RQL) processor.
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- Date: 23 Apr 2019
- Time: 06:30 PM to 08:30 PM
- All times are (UTC-04:00) Eastern Time (US & Canada)
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- University of Maryland
- 8223 Paint Branch Dr.
- College Park, Maryland
- United States 20742
- Building: A. V. Williams Bldg.
- Room Number: Rm. 2460
- Click here for Map
- Contact Event Host
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nfhaddad@aol.com
murtyp@ieee.org
paul.potyraj@ngc.com
- Co-sponsored by Electron Devices Society/Baltimore Chapter
- Starts 21 March 2019 07:00 PM
- Ends 22 April 2019 07:00 PM
- All times are (UTC-04:00) Eastern Time (US & Canada)
- No Admission Charge
Speakers
Michael J. Vesely of Northrop Grumman, Linthicum, MD
A Pipelined Superconducting 16-bit CPU Design
A primary goal of superconducting logic research is the development of more advanced processor architectures that are capable of efficiently performing longer, more complex tasks. In pursuit of this, we designed an 8-bit CPU, which demonstrated the feasibility of a Reciprocal Quantum Logic (RQL) processor. Here we present a 16-bit RQL CPU design that continues the development of superconducting electronics and is capable of improved performance. This CPU features a pipelined Harvard architecture and supports 72 instructions with 1 Kbyte of non-destructive read out (NDRO)-based memory. The CPU architecture includes a Turing complete instruction set that supports logical operations, addition, subtraction, comparison, barrel shifts, as well as immediate type operations and relative branching.
The requirements of the CPU architecture drives the development of new technology capabilities. The most prominent new capability in the 16-bit CPU design is the use of RQL-tuned, scalable commercial tools for fully automated synthesis, placement, routing, and verification of the entire logic portion of the processor. An expanded gate library, which includes new 3- and 4-input gates enables an improved optimization of area and performance. The 16-bit RQL CPU also implements passive transmission lines for reduced latency in block-to-block interconnect. As a result of these developments, the 16-bit RQL CPU has an average of four clocks per instruction (CPI), and represents a 10X improvement in performance over the 8-bit RQL CPU described in prior literature.
Multiple individual subcomponents, such as the ALU and memory banks, have already been fabricated, tested, and demonstrated to be fully functional. The complete 16-bit RQL CPU is planned for fabrication in the D-Wave superconducting process and for testing this year.
Biography:
Michael J. Vesely is an integrated product team technical lead for the Cryogenic Computer Complexity (C3) program at Northrop Grumman. Since joining Northrop Grumman in 2015, Mike has worked on a multidisciplinary team developing the first general purpose superconducting Reciprocal Quantum Logic (RQL) based central processing units (CPUs). RQL based CPUs are a low power alternative, and provide a path towards exascale computing in an era where power and cooling for CMOS based supercomputing is becoming unmanageable due to increasing computation requirements. In addition to leading chip level integration efforts, Mike’s work has focused on fabrication process development, architecture definition, physical design, and EDA tool development as specific to RQL. Prior to joining Northrop Grumman, Mike was a part of the system validation team at the Intel Corporation developing digital, electrical, and thermal validation platforms for the Xeon server and Atom mobile processor families. Mike received his Bachelor’s and Master’s degrees in Computer Engineering from the University of Maryland, Baltimore County in 2008 and 2010.
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Dr. Ian M. Dayton of Northrop Grumman, Linthicum, MD
Demonstration of JMRAM Arrays
Superconducting circuits are under development as a solution to the demand for ultralow power computers. Logic technologies based in superconducting materials, such as Reciprocal Quantum Logic (RQL) require the development of a superconducting memory in order to build complex computers. Josephson Magnetic Random Access Memory (JMRAM) is a non-volatile memory utilizing the 0-π phase characteristics of pseudo-spin valve magnetic barrier Josephson junctions as a phase element within more traditional superconductor-insulator-superconductor (SIS) SQUIDs, which are used to read the phase state. Here, we present the first successful demonstration of JMRAM from a single unit cell to 2x2 and 8x8 arrays. All arrays are built based on Ni/Cu/NiFe pseudo-spin valve junctions with 50-100 Oe switching field and high critical current of 0.5 mA. All array elements were functional with 100% switching between 0 and 1 state using external magnetic fields. This foundational demonstration serves as the basis for a more complete assessment of the progress of this technology toward practical implementation.
Biography:
Ian M. Dayton received his Bachelor’s degree in Engineering Physics from the University of Illinois at Urbana-Champaign in 2012 and his Ph.D. in Physics from Michigan State University in 2016. His thesis work focused primarily on the study of the superconducting proximity effect in exotic materials known as topological insulators (TI). Superconductor/TI systems are predicted to play an integral role in future spintronic devices as well as the world of quantum computing. After joining Northrop Grumman in 2017, Ian has worked with a team developing cryogenic memory known as Josephson Magnetic Random Access Memory (JMRAM), which consists of superconductor/ferromagnet heterostructures that utilize very similar physics to superconductor/TI systems. Currently, he is the lead for the functional and JMRAM test labs in the Cold Logic program at Northrop Grumman.
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Agenda
6:30 PM - 7:00 PM Arrivals and Networking
7:00 PM - 7:05 PM Announcements and Introduction of Speakers
7:05 PM - 8:00 PM Presentations
8:00 PM - 8:15 PM Questions and Answers
This research is based upon work supported by the ODNI, IARPA, via ARO contract number W911NF-14-C-0115. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the ODNI, IARPA, or the U.S. Government.