Ihsan Erdin of Celestica

For multicore processors with current loads exceeding 100 A, the power noise is not only a growing electromagnetic interference (EMI) concern, but also a potential logic problem in high-speed printed circuit designs. Depending on the type of application, onboard or on-package local decoupling capacitors are the most commonly used components to mitigate this problem. The board/ package real-estate concerns, however, impede the haphazard placement of these components and makes imperative the use of optimization methods for their most effective placement and selection. The computation of power noise in high-speed designs lies at the core of all optimization techniques. For decades, the computation methods that rely on lumped circuit theory have been very popular as quick and dirty analysis tools. At today's circuit speeds, however, they are too simplistic for accurate results. Numerical electromagnetic analysis tools are arguably the reliable alternatives but they are computationally too intensive for repetitive analysis. Semi-analytic algorithms based on planar circuit theory will be discussed as a balance between these two extreme cases. Accuracy and performance comparison with state-of-the art tools will be provided. The practical implications of these methods will be discussed with application to real-life scenarios.

Biography:

Ihsan Erdin received the M. Sc. degree from Middle East Tech. U, Ankara, Turkey in 1993 and the Ph.D. degree from Carleton University in 2001, both in electrical engineering. From 1995 to 1996, he was a research fellow at Defense Research Development (DRDC) Ottawa. From 2000 to 2007.  Dr. Ihsan Erdin is the Engineering Design Manager and SI/PI subject matter expert at Celestica. His primary job function is Celestica’s global SI/PI/EMC subject matter expert on product development and technical services. The responsibilities also include mentoring and providing technical support to the SI/PI design and analysis team. He has 20 years of experience in signal and power integrity design of multi-gigabit rate ATCA core and edge routers, including Metro Ethernet, ATM, MPLS and Carrier Ethernet line cards/ backplanes. He is an expert in timing, jitter and power/signal integrity analysis of high-speed serial and parallel interfaces as well as power and still-air thermal analysis of printed circuit structures with an in-depth knowledge of electromagnetic theory, expert on transmission lines, microwave/EMI filters as well as grounding techniques for challenging mixed-analog/digital systems. He has published over 30 journal and conference papers on electromagnetic analysis of printed circuit structures with particular emphasis on signal and power integrity. Dr. Erdin has authored over 150 signal and power integrity reports for a variety of customers including IBM, Microsoft, CISCO, Ciena, DirecTV, NEC, Juniper and others. Following is a summary of his presentation options:

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Address:Ottawa, Ontario, Canada