Seminar on ESD (basics, circuits, techniques)

#ESD #microelectronics #circuits #protection
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2-day seminar on ESD given by dr Charvaka Duvvury. Details can be found in the agenda.



  Date and Time

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  • AGH University of Science and Technology
  • Av. Mickiewicza 30
  • Cracow, Malopolskie
  • Poland 30-059
  • Building: B-1
  • Room Number: H-24 lecture hall

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  • Co-sponsored by Silicon Creations


  Speakers

Charvaka Duvvury

Biography:

Charvaka Duvvury received his PhD in Engineering Science from the University of Toledo and afterwards worked as a post-doctoral fellow in Physics at the University of Alberta in Edmonton, Canada, before joining Texas Instruments during 1977. His experience at TI spanned for 35 years in semiconductor device physics with development work in ESD design. He was elected as TI Fellow in 1997 and as IEEE Fellow during 2008. He has also mentored PhD students at several leading US universities on their investigations in ESD research. He has contributed to the industry by offering tutorials at IEEE sponsored conferences, as an organizer/instructor of the Berkeley Extension ESD Short Course for over a decade, and as a participant in the EDS DL Program.  

He is currently working as a technical consultant on ESD design. He is a recipient of the IEEE Electron Devices Society’s Education Award (2013), Outstanding Contributions Award from the EOS/ESD Symposium (1990), and Outstanding Industry Mentor Award from the Semiconductor Research Council (1994 and 2012).  From 2004-2006 he served on the IEDM CMOS Reliability Sub-committee, and during 2001-2011 served as editor of the IEEE-TDMR. He has published over 150 papers in technical journals and conferences and holds US 75 patents. He co-authored and contributed to 5 books. Charvaka has been serving on Board of Directors of the ESD Association (ESDA) since 1997 promoting ESD education and research at academic institutes. He served twice as General Chairman of the ESD Symposium. He is co-founder and co-chair of the Industry Council on ESD since 2006. During 2015 he became a co-founder of the iT2 Technologies that utilizes software engine for rapid ESD data analysis.





Agenda

Day 1 

9:00 to 9:30: Fundamentals of ESD, EOS, Latchup . ESD vs. IC Reliability 

9:30 to 10:30: ESD in Manufacturing. ESD Stress Models. ESD Test Standards. ESD Physics and High Current Behavior. ESD Characterization with Pulse Testing 

10:30 to 11:00 Coffee Break 

11:00 to 12:30: Process Technology Effects. Basic Protection Designs for HBM/CDM. Methods for ESD Layout and Optimization. Latchup Design and Layout Optimization. Failure Analysis and Lessons Learned  

12:30to 14:00 Lunch Break 

14:00 to 15:30: Advanced Protection Design Options. Capacitance Trade-off. Simulations of Protection Clamps. Analog Designs. Chip ESD Design Techniques 

15:30 PM to 16:00 Coffee Break 

16:00 to 16:30: RF Designs. Mixed Voltage and High Voltage Designs.

16:30 to 17:30: Advanced Technology Effects . High Speed IO Protection. CDM Package Effects and Design Optimization. 

 

Day 2 

9:00 to 9:30 Review of Day 1 Concepts 

9:30 to 10:30: FinFET Technology and ESD Design
10:30 to 11:00: Coffee Break

11:00 to 12:00: SOI ESD Elements. SOI ESD Design Methods.

12:00 to 12:30: System Level ESD with IC Interface. On-Chip vs, Off-Chip System Protection. USB/HDMI Protection, and Antenna Protection. EOS Effects. Good Design Principles.