IEEE Swiss SSC Talks : Circuit and Device implications for Reliable Flash and Phase Change Memory

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Non volatile memory is not only the ubiquitous storage medium in consumer applications but has also started to appear in enterprise storage systems as well.

Flash technology made it possible to store multiple bits in the same silicon area, thus reducing the cost per amount of data stored. However, at current sub-20nm technology nodes, flash devices fail to provide the levels of raw reliability, mainly cycling endurance, that are required by typical enterprise applications.

Advanced signal processing and coding schemes are needed to improve the flash bit error rate and thus elevate the device reliability to the desired level. In this article, we report on the use of adaptive voltage thresholds and cell-to-cell interference cancellation in the read operation of NAND flash devices.

Fields of research touch each other and overlap. Innovative material and devices such as Phase Change memory PCM has already seen 10-15 years of intense research, and recently advanced development in the labs of most memory manufacturers.

While these alternative technologies are mostly still in the basic research stage. In terms of characteristics, memristors are thought to be an eventual replacement for Flash memory due to their potentially better scalability and performance. However, their limited capability for multi-level cell storage might limit their price competitiveness in cost per gigabyte.

This seminar discuss on the Circuits and Device implications for Reliable Flash and Phase Change Memory.



  Date and Time

  Location

  Contact

  Registration



  • EPFL
  • 71, Rue de la Maladière
  • Neuchatel, Switzerland
  • Switzerland CH-2000
  • Building: Microcity
  • Room Number: MC B1 273
  • Starts 10 September 2019 10:00 AM
  • Ends 01 October 2019 12:00 AM
  • All times are Europe/Zurich
  • No Admission Charge
  • Register


  Speakers

Haris Pozidis of IBM Research

Topic:

Circuit and Device implications for Reliable Flash and Phase Change Memory

Biography:

Haris Pozidis received a B.S. degree in Computer Engineering and Informatics from the University of Patras, Greece, in 1994, and M.Sc. and Ph.D. degrees in Electrical Engineering from Drexel University, Philadelphia, U.S.A., in 1997 and 1998, respectively.

Between 1998 and 2001 he was with Philips Research, Eindhoven, The Netherlands, where he worked on read channel design for DVD and Blu-ray Disc optical recording formats. In 2001 he joined IBM Research – Zurich, Switzerland, to work on recording technology, signal processing and system-level design for scanning-probe data-storage devices.

He currently manages the Cloud Storage and Analytics group at the Zurich laboratory, which focuses on the development of Flash memory controllers for all-flash arrays, on novel nonvolatile memory technology-based system concepts, and on the design of algorithms for scalable, accelerated machine learning.

Dr. Pozidis holds over 105 US and European patents in the areas of solid-state memory technology, probe-based data storage, control systems technology and optical data storage.

In 2009, we was co-recipient of the IEEE Control Systems Technology Award and the IEEE Transactions on Control Systems Technology Outstanding Paper Award. He is an IBM Principal Research Scientist, an IBM Master Inventor, and a Senior Member of the IEEE.

Email:

Address:IBM Research - Zurich, Säumerstrasse 4, , Rüschlikon, Switzerland, Switzerland, 8803