Dr. Brajesh Kumar Kaushik of Indian Institute of Technology, Roorkee, India

Conventional CMOS technology has reached to the brink of its scaling limits and poses significant challenges for the development of next generation high-speed ultra-low power cost-effective memory and processing devices. The failure of Moore's law on the technology roadmap has enforced the research community to explore alternative technology solutions to mitigate the problems. In the post-CMOS era, spintronics shall emerge as a potentially viable interdisciplinary field with credible technological perspectives. Spintronic exploits an electron’s spin orientation and its associated magnetic moment as a state variable instead of a conventionally used charge in CMOS technology. In general, the spintronic devices are layered structure of ferromagnetic materials and provide the nonvolatile storage options and manipulations of logic states. Spin transfer torque (STT) and spin orbit torque (SOT) devices using magnetic tunnel junctions (MTJs) have become strong contenders for the nonvolatile embedded memory architectures with the capability of implementing the concepts of "logic-in-memory" and "material-device-circuit co-design." The spin torque devices offer the features of "universal memory" i.e., high speed, non volatility, high density, and low power, high endurance, CMOS process compatibility. Apart from the basic spin torque devices, the field of spintronics encloses all

spin logic (ASL) devices, domain wall (DW) based devices, spin diodes, and spin FETs. The material and device level roadmaps for the field of spintronicssuggest that the research work is at the infant stage and still require different elemental spin device developmentswith the understanding of associated underlying physics. In addition, the accurate models for the spintronic devices imitating the effect of stochastic behaviour and PVT variations need to be explored. Spintronics based architectures are being considered for computing applications such as bio-inspired computing and quantum computing. These spintronics based novel computing approaches find applications in image processing and provides efficient solution to the complex computing problems.

Biography:

Dr. Brajesh Kumar Kaushik (SM'13) received Doctorate of Philosophy (Ph.D.) in 2007 from Indian Institute of Technology, Roorkee, India. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been an Associate Professor. He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is a Senior Member of IEEE and member of many expert committees constituted by government and non-government organizations. He is Editor of IEEE Transactions on Electron Devices; Associate Editor of IET Circuits, Devices & Systems; Editor of Microelectronics Journal, Elsevier; Editorial Board member of Journal of Engineering, Design and Technology, Emerald and Circuit World, Emerald. He has received many awards and recognition from the International Biographical Center (IBC), Cambridge. His name has been listed in Marquis Who’s Who in Science and Engineering® and Marquis Who’s Who in the World®. Dr. Kaushik has been conferred with Distinguished Lecturer (DL) award of IEEE Electron Devices Society (EDS) to offer EDS Chapters with quality lectures in his research domain. He also serves as Visiting Lecturer of SPIE society to deliver lectures in the area of Spintronics and Optics. He has 12 books to his credit published by reputed publishers such as CRC Press, Springer, Artech and Elsevier. One his authored books titled “Nanoscale  Devices: Physics, Modeling, and Their Application”, CRC Press has won 2018 Outstanding Book and Digital Product Awards in the Reference/Monograph Category from Taylor and Francis Group. His research interests are in the areas of high-speed interconnects, low-power VLSI design, memory design, carbon nanotube-based designs, organic electronics, FinFET device circuit co-design, electronic design automation (EDA), spintronics-based devices, circuits and computing, image processing, and optics & photonics based devices.

Email:

Address:Department of ECE, Indian Institute of Technology, Roorkee, Uttarakhand , Uttaranchal, India, 247667

Dr Mayank Shivastava of Indian Institute of Science Bangalore, India

Like petroleum, electronics has become a key driver for major economies in the world. For instance, at the commercial front, China has (recently) become the biggest exporter of electronics/semiconductor products in the world. Taiwan’s major business is in Semiconductors, which is one of the key drivers of their economy. Similarly, India’s electronics import is at the verge of exceeding its oil import. At the strategic front, often the technological capabilities are driven by electronic / semiconductor technologies available in-house. In this context, India has attempted several times, in last two decades, to catch the bus in terms of setting-up a silicon CMOS foundry, which can cater to India’s commercial, strategic and scientific needs. For all practical reasons, if India attempts to catch-up the west in technologies having very high obsolescence rate, India may not be able to take a lead in future. In this context, the question is, “How India can take a lead – at the international front - in Semiconductor R&D, leading to commercial and strategic independence”? Speaker of this talk believes that for India to become a leader, India must jump the technology roadmap and rather than only catching-up on the established technologies, invests pro-actively on disruptive technologies projected for future. This talk will be pitched with the vision and belief highlighted above, while discussing 5 key disruptive technologies, which can be game changers as far as future of electronics is concerned.

Biography:

Prof. Mayank Shrivastava received his PhD degree from Indian Institute of Technology Bombay. For his PhD work he received excellence in research award for his PhD thesis in 2010 and industrial impact award from IIT Bombay in 2008. He is among the first recipients of Indian section of American TR35 award (2010) and the first Indian to receive IEEE EDS Early Career Award (2015). Besides, he is an IEEE Senior Member and has received several other national awards and honours of high repute, like National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018; Indian National Academy of Science (INSA) Young Scientist Award - 2018; Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation); Indian National Academy of Engineering (INAE) Young Engineer Award - 2017; INAE Young Associate (since 2017); Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023; Department of Electronics & Information Technology (DeitY), Young Faculty Fellowship.  He has received best paper awards from several international conferences like Intel Corporation Asia academic forum; VLSI design conference and EOSESD Symposium. Prof. Shrivastava’s current research deals with experimentation, design and modelling of beyond CMOS devices using Graphene and TMDCs, wide bandgap material based power semiconductor devices and ESD reliability in advanced and beyond CMOS nodes. He had held visiting positions in Infineon Technologies, Munich, Germany from April 2008 to October 2008 and again in May 2010 to July 2010. He worked for Infineon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; and Intel Corp., Mobile and Communications Group, Munich, Germany between 2010 and 2013. He joined Indian Institute of Science as a faculty member in year 2013 where he is currently working as an Associate Professor. Prof. Shrivastava has over 110 peer reviewed international publications and 40 patents.

Email:

Address:Dept. of Electronic Systems Engineering, IISc, Bangalore, Karnataka, India, 560012