Advanced Frequency Synthesis For Digitally Intensive Transmitters For IoT And Mm-Wave Radios, CASS-SCV Multi-Speaker Event

#Digital #PLLs #IoT #5G #mm-Wave #Radios #Time #Mode #ADC #Sub-threshold #Circuit #Design
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Advanced Frequency Synthesis For Digitally Intensive Transmitters For IoT And Mm-Wave Radios, CASS-SCV Multi-Speaker Event

Dr. Robert Bogdan Staszewski, School of Electrical & Electronic Engineering, University College Dublin and

Dr. Yizhe Hu, School of Electrical & Electronic Engineering, University College Dublin

Event Organized By:

Circuits and Systems Society (CASS-SCV) of the IEEE Santa Clara Valley Section

Co-sponsors:

PROGRAM:

5:30 - 6:00 PM Networking & Refreshments

6:00 - 6:50 PM Lecture 1: "Deep-Subthreshold Operation of ADPLLs, Transmitters and ADCs," by Dr. Robert Bogdan Staszewski

6:50 - 7:00 PM Q&A

7:00 - 7:50 PM Lecture 2: "A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sharing Locking," by Dr. Yizhe Hu

7:50 - 8:00 PM Q&A/Adjourn

Lecture 1 (6:00 - 6:50 PM): "Deep-Subthreshold Operation of ADPLLs, Transmitters and ADCs," by Dr. Robert Bogdan Staszewski

Abstract:

Internet-of-Things (IoT) devices are meant to be powered by energy harvesters, which unfortunately tend to generate very little power at very low voltages, often well below the threshold voltage of CMOS transistors. Hence the need for an ultra-low power (ULP) and ultra-low voltage (ULV) operation of IoT electronic circuits. This talk presents recent breakthroughs in collaboration with TSMC in sub-threshold designs of an all-digital PLL (ADPLL), RF Bluetooth transmitter, and open-loop VCO-based ADC. The supply voltage in these circuits can go to as low as 0.2V.

Bio:

  1. Bogdan Staszewskireceived B.Sc. (summa cum laude), M.Sc. and PhD from University of Texas at Dallas, USA, in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel in Richardson, Texas. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co-started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is currently a part-time Full Professor. Since Sept. 2014 he has been a Full Professor at University College Dublin (UCD) in Ireland. He has co-authored five books, seven book chapters, 300 journal and conference publications, and holds 180 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers, as well as quantum computers. He is a co-founder of a startup company Equal1 Labs aiming at building the first practical CMOS quantum computer.

He is an IEEE Fellow and a recipient of IEEE Circuits and Systems Industrial Pioneer Award (http://ieee-cas.org/industrial-pioneer-award-recipients). He was a TPC Chair of IEEE European Solid-State Circuits Conference (ESSCIRC) in 2019 in Krakow, Poland.

Lecture 2 (7:00 - 7:50 PM): "A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sharing Locking," by Dr. Yizhe Hu

Abstract:

Ultra-low jitter (sub-100fs) frequency synthesis is highly desirable for 5G RF and mm-Wave (mmW) communications to support the complex modulation schemes (e.g. 1024QAM). Our group has recently invented a new charge-sharing locking (CSL) technique to meet these tough requirements. A quadrature CSL prototype was implemented in TSMC 28nm CMOS and achieves 75fs jitter in 21.7-to-26.5GHz while consuming only 16.5mW. This talk presents the details and gives further insights into designing oscillators with ultra-low phase noise in the flicker and thermal regions.

Bio:

Yizhe Hu received the B.Sc. degree (summa cum laude) in microelectronics from Harbin Institute of Technology (HIT), Harbin, China, in 2013, and the PhD degree in microelectronics from University College Dublin (UCD), Dublin, Ireland, in 2019. He is currently working as a postdoctoral researcher with Prof. R. Bogdan Staszewski in UCD. From 2013 to 2014, he was with Fudan University, Shanghai, China, where he was involved in RFIC design as a postgraduate researcher. From May 2016 to Oct 2017, he was consulting for the PLL Group of HiSilicon, Huawei Technologies, China, designing 16 nm DCOs and ADPLLs. Since June 2018, he has been consulting for the Mixed-Signal Design Department, TSMC, for a new type of PLL design. His research interests include RF/mm-wave integrated circuits and systems for wireless communications. Dr. Hu has served as a frequent reviewer for the IEEE JSSC, TCAS-I/II, and TMTT.

Zoom Broadcast:

Lecture will be broadcast live on Zoom and recorded. Please register to receive Zoom conference details one day before the event.

Venue:

QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.


  Date and Time

  Location

  Hosts

  Registration


  • Date: 20 Feb 2020
  • Time: 05:30 PM to 08:00 PM
  • All times are (GMT-08:00) US/Pacific
  • Add_To_Calendar_icon Add Event to Calendar
  • QualComm Santa Clara
  • 3165 Kifer Road
  • Santa Clara, California
  • United States 95051
  • Building: Building B
  • Click here for Map
  • Contact Event Host
  • Co-sponsored by Solid State Circuits Society (SSCS), Microwave Theory and Techniques Society (MTT), Communication Society (ComSoC), Signal Processing Society (SPS)

  Speakers

Robert Bogdan Staszewski Robert Bogdan Staszewski of University College Dublin

Topic:

Deep-Subthreshold Operation of ADPLLs, Transmitters and ADCs

Internet-of-Things (IoT) devices are meant to be powered by energy harvesters, which unfortunately tend to generate very little power at very low voltages, often well below the threshold voltage of CMOS transistors. Hence the need for an ultra-low power (ULP) and ultra-low voltage (ULV) operation of IoT electronic circuits. This talk presents recent breakthroughs in collaboration with TSMC in sub-threshold designs of an all-digital PLL (ADPLL), RF Bluetooth transmitter, and open-loop VCO-based ADC. The supply voltage in these circuits can go to as low as 0.2V.

Biography:

  1. Bogdan Staszewskireceived B.Sc. (summa cum laude), M.Sc. and PhD from University of Texas at Dallas, USA, in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel in Richardson, Texas. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co-started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is currently a part-time Full Professor. Since Sept. 2014 he has been a Full Professor at University College Dublin (UCD) in Ireland. He has co-authored five books, seven book chapters, 300 journal and conference publications, and holds 180 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers, as well as quantum computers. He is a co-founder of a startup company Equal1 Labs aiming at building the first practical CMOS quantum computer.

He is an IEEE Fellow and a recipient of IEEE Circuits and Systems Industrial Pioneer Award (http://ieee-cas.org/industrial-pioneer-award-recipients). He was a TPC Chair of IEEE European Solid-State Circuits Conference (ESSCIRC) in 2019 in Krakow, Poland.

Dr. Yizhe Hu of University College Dublin

Topic:

A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sharing Locking

Ultra-low jitter (sub-100fs) frequency synthesis is highly desirable for 5G RF and mm-Wave (mmW) communications to support the complex modulation schemes (e.g. 1024QAM). Our group has recently invented a new charge-sharing locking (CSL) technique to meet these tough requirements. A quadrature CSL prototype was implemented in TSMC 28nm CMOS and achieves 75fs jitter in 21.7-to-26.5GHz while consuming only 16.5mW. This talk presents the details and gives further insights into designing oscillators with ultra-low phase noise in the flicker and thermal regions.





Agenda

Advanced Frequency Synthesis For Digitally Intensive Transmitters For IoT And Mm-Wave Radios, CASS-SCV Multi-Speaker Event

Dr. Robert Bogdan Staszewski, School of Electrical & Electronic Engineering, University College Dublin and

Dr. Yizhe Hu, School of Electrical & Electronic Engineering, University College Dublin

Event Organized By:

Circuits and Systems Society (CASS-SCV) of the IEEE Santa Clara Valley Section

Co-sponsors:

PROGRAM:

5:30 - 6:00 PM Networking & Refreshments

6:00 - 6:50 PM Lecture 1: "Deep-Subthreshold Operation of ADPLLs, Transmitters and ADCs," by Dr. Robert Bogdan Staszewski

6:50 - 7:00 PM Q&A

7:00 - 7:50 PM Lecture 2: "A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sharing Locking," by Dr. Yizhe Hu

7:50 - 8:00 PM Q&A/Adjourn

Lecture 1 (6:00 - 6:50 PM): "Deep-Subthreshold Operation of ADPLLs, Transmitters and ADCs," by Dr. Robert Bogdan Staszewski

Abstract:

Internet-of-Things (IoT) devices are meant to be powered by energy harvesters, which unfortunately tend to generate very little power at very low voltages, often well below the threshold voltage of CMOS transistors. Hence the need for an ultra-low power (ULP) and ultra-low voltage (ULV) operation of IoT electronic circuits. This talk presents recent breakthroughs in collaboration with TSMC in sub-threshold designs of an all-digital PLL (ADPLL), RF Bluetooth transmitter, and open-loop VCO-based ADC. The supply voltage in these circuits can go to as low as 0.2V.

Bio:

  1. Bogdan Staszewskireceived B.Sc. (summa cum laude), M.Sc. and PhD from University of Texas at Dallas, USA, in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel in Richardson, Texas. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co-started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is currently a part-time Full Professor. Since Sept. 2014 he has been a Full Professor at University College Dublin (UCD) in Ireland. He has co-authored five books, seven book chapters, 300 journal and conference publications, and holds 180 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers, as well as quantum computers. He is a co-founder of a startup company Equal1 Labs aiming at building the first practical CMOS quantum computer.

He is an IEEE Fellow and a recipient of IEEE Circuits and Systems Industrial Pioneer Award (http://ieee-cas.org/industrial-pioneer-award-recipients). He was a TPC Chair of IEEE European Solid-State Circuits Conference (ESSCIRC) in 2019 in Krakow, Poland.

Lecture 2 (7:00 - 7:50 PM): "A New Type of Frequency Synthesis for RF and mm-Wave: Charge-Sharing Locking," by Dr. Yizhe Hu

Abstract:

Ultra-low jitter (sub-100fs) frequency synthesis is highly desirable for 5G RF and mm-Wave (mmW) communications to support the complex modulation schemes (e.g. 1024QAM). Our group has recently invented a new charge-sharing locking (CSL) technique to meet these tough requirements. A quadrature CSL prototype was implemented in TSMC 28nm CMOS and achieves 75fs jitter in 21.7-to-26.5GHz while consuming only 16.5mW. This talk presents the details and gives further insights into designing oscillators with ultra-low phase noise in the flicker and thermal regions.

Bio:

Yizhe Hu received the B.Sc. degree (summa cum laude) in microelectronics from Harbin Institute of Technology (HIT), Harbin, China, in 2013, and the PhD degree in microelectronics from University College Dublin (UCD), Dublin, Ireland, in 2019. He is currently working as a postdoctoral researcher with Prof. R. Bogdan Staszewski in UCD. From 2013 to 2014, he was with Fudan University, Shanghai, China, where he was involved in RFIC design as a postgraduate researcher. From May 2016 to Oct 2017, he was consulting for the PLL Group of HiSilicon, Huawei Technologies, China, designing 16 nm DCOs and ADPLLs. Since June 2018, he has been consulting for the Mixed-Signal Design Department, TSMC, for a new type of PLL design. His research interests include RF/mm-wave integrated circuits and systems for wireless communications. Dr. Hu has served as a frequent reviewer for the IEEE JSSC, TCAS-I/II, and TMTT.

Zoom Broadcast:

Lecture will be broadcast live on Zoom and recorded. Please register to receive Zoom conference details one day before the event.

Venue:

QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.