A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol
In this presentation Dr. Bichan from Intel - Toronto goes over their recent publication at CICC2020 titled "A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol". The presentation will be followed by Q&A.
Introduction: Growing data center bandwidth demand increases the need for fast wireline transmission. One of the key protocols used to transfer data between SoC’s is PCI Express. The recently published PCI Express Gen 5 standard allows data transmission at up to 32 Gb/s. The practical design requirements for a PCI Express Gen 5 PHY IP go beyond protocol compliance. Other considerations include: small IP area, die-edge dimension, and power to allow large numbers of data links in a single SoC, large dynamic temperature range for extreme environmental conditions, advanced power management to reduce power when the link is not in use, low data path latency to improve overall system performance, and robust performance with internal adaptive equalization. This paper presents the first SerDes design to demonstrate a PCI Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and clocking, power management including power gating for all analog blocks, continuous data rate support between 1-32Gb/s, and supporting channel topologies with insertion loss up to 37dB at 16GHz with BER < 1e-12 in 10nm process technology.
Date and Time
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- Date: 14 May 2020
- Time: 05:10 PM to 06:00 PM
- All times are (GMT-05:00) US/Eastern
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- Toronto, Ontario
- Canada
- Starts 05 May 2020 06:50 PM
- Ends 14 May 2020 06:50 PM
- All times are (GMT-05:00) US/Eastern
- No Admission Charge
Speakers
Mike Bichan of Intel, Toronto
Biography:
Dr. Mike Bichan completed the Ph.D. degree at the University of Toronto. He began working at Toronto startup V Semiconductor Inc. in 2009. After Vsemi’s acquisition by Intel in September 2012, Mike was instrumental in creating SerDes IP for Intel in 22, 14, and 10nm. Mike is currently Principal Engineer at Intel, leading a team of analog circuit designers. Since developing the first PCIe Gen5 PHY, Mike has focused on the development of analog-based 58Gbps PAM SerDes IP for networking applications. This IP is targeted at a broad range of standards and meets the requirements for PCIe, Ethernet, OIF, CPRI, JESD, USB, SATA, GPON, HDMI, DisplayPort, OTN, SDI, and SONET.