Jeffrey Dunnihoo of Pragma Design

Since the introduction of the Field Collapse Event (FCE: Dunnihoo, Tamminen, Viheriäkoski 2015) testing improvements over Charged Board Events (CBE), Pragma Design has continued to apply and adapt this methodology to other ESD/EOS/EMC domains. While high-voltage referenced CBE is a real and distinct ESD aggressor in manufacturing and in the field, FCE methods allow functional and powered testing with similar real-world pulses while the system under test remains at a safe ground potential. Combining this new method together with fully automated near field scanning equipment to construct E- and H-field information of a system during transient ESD events is described. This inexpensive method provides an alternative way for system designers to validate and analyze the EMC/ESD robustness of electronic systems without TLP pulsers, IEC61000-4-2 guns, or precision inductive current probes.

Biography:

Jeffrey Dunnihoo is the founder of Pragma Design specializing in interface design architecture and ESD, EOS, and other transient analysis, and he also collaborates with Dangelmayer Associates for system and factory consulting issues. These engineering services are based on decades of experience in I/O ASIC and serial bus interface protection and design. Pragma Design's current PESTO online ESD simulation tool implements the Industry Council's system efficient ESD design methodology which is used in Littelfuse's iDesign simulation tool. Jeff has presented at IEEE EMC, ESDA, ISTFA, and has co-authored a new textbook with other ESD experts on ESD co-design fundamentals, as well as a series of children's books about engineering.

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