Lecture on "Advanced Digital Design-1"
A session was taken up by Ms. Sahithya, Assistant Professor of VNRVJIET on the Techniques of Digital Logic Design on 10th of June from 11 AM to 1 PM.
1. The session started off with a basic recap of previous session and explanation of why the industry prefers digital design, what are its advantages and disadvantages. She spoke about the intrusion of noise and the advantages in terms of power consumption.
2. Next, the speaker moved on to the explanation of the levels of abstraction included in digital design, and spoke about programs, device drivers, instruction registers, datapaths controllers, adders, memories, AND and NOT gates, Amplifiers, Filters, Transistors, Diodes and the role of electrons.
3. The number system was explained and different conversions were taught with the help of examples and the importance of it was explained.
4. Logic gates and their functions were taught in detail.
5. Combinational circuits like multipliers, encoders, decoders, comparators and the minimisation using Karnaugh maps was explained.
6. Last but not the least, glitches and timing diagrams were demonstrated. The meaning of delay, set up and hold time were explained in detail.
Date and Time
Location
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- Date: 10 Jun 2020
- Time: 11:00 AM to 01:00 PM
- All times are (UTC+05:30) Chennai
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- Hyderabad, Andhra Pradesh
- India
Speakers
Mrs G Sahithya of VNR Vignana Jyothi Institute of Engineering and Technology
Digital Logic Design
Biography:
Assistant Professor
Email:
Agenda
After the lecture on VLSI Recent Trends in the Industry, a session on the Fundamental Digital Logic Design was held on June 10th, 2020.
A total of around 50 students participated in the session and utilized this opportunity to brush up their knowledge on the digital design flow which they learnt in the 2nd year of their curriculum.
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| SS2 | 98.45 KiB | |
| SS3 | 233.37 KiB |