Lecture on "Classification of IC Design"

#CPLD #PLD #FPGA #ASIC #ASSP
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A lecture on "Classification of IC Design" was delivered by Mr K Sarath Chandra on 16th of June, 2020.

The session covered a vast range of topics which also included the criteria an engineer looks for while designing a circuit and what are the advantages of one type over other. The difference between ASSP, ASIC and FPGA was explained.

The working of Programmable Logic Devices (PLD) was explained along with a few examples like MAX7000 CPLD.

CPLD and its applications in optical encoders, bus protocol translation, memory controllers, data acquisition control was explained.

The structure of Look-up tables (LUTs) along with examples were explained and programming technologies like fuse and anti-fuse was explained.

 


  Date and Time

  Location

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  Registration


  • Date: 16 Jun 2020
  • Time: 11:00 AM to 01:00 PM
  • All times are (UTC+05:30) Chennai
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  • Hyderabad, Andhra Pradesh
  • India
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  Speakers

Mr K Sarath Chandra Mr K Sarath Chandra of VNR Vignana Jyothi Institute of Engineering and Technology

Topic:

Classification of IC Design

Biography:

Assistant Professor, Dept. of ECE

Teaching Interests: VLSI Design, Pulse and Digital Circuits, , Analog Communications, Electronic devices & Circuits, Basic Electronics CMOS Analog IC Design, CMOS Mixed Signal IC Design, Electronic Circuit Analyses




Agenda

This lecture was organised in order to tell the differences between different ICs and their classification such as CPLD, PLD and FPGA.


With a participation of 45 students, the response was tremendous as the students asked a number of questions towards the end of the session.


  Media

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