Lecture on "Importance of Verilog HDL in Digital Design Automation"

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On 18th June, 2020 Ms. K Swetha Reddy gave a lecture on the topic “Importance of Verilog HDL in Digital Design Automation".

Ms. K Swetha Reddy started the webinar by explaining the students the main purpose of Verilog that is to convert the digital circuits into language format in the same way as we develop our applications in C and other programming languages.

The speaker then explained about the process of VLSI design flow which starts from idea to specifications, design architecture, RTL coding , RTL verification, synthesis, device layout, placement and routing, mask layout , foundary which ends at IC chip.

History and types of HDL (VHDL, Verilog HDL, system verilog) were explained in brief.

Then the speaker showed us the difference between Verilog and VHDL and explained why verilog is better than VHDL in lower level hardware modeling. It is because Verilog is originally created for modeling and simulating logic gates. And at system level VHDL is better than Verilog.

Design methodology which is the protocol to design the architecture in HDL language was explained followed by the levels of abstraction which are switch level, gate level,data flow level and behavioural level.

Then the session went on to explain about modules and ports,registers, delays and operators and a brief information on lexical conventions was given.

At last, the speaker gave a recap of all the concepts she covered in the lecture so far and what to expect in the next lecture and ended the session.


  Date and Time

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  • Date: 18 Jun 2020
  • Time: 11:00 AM to 01:00 PM
  • All times are (UTC+05:30) Chennai
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  • Hyderabad, Andhra Pradesh
  • India
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  Speakers

Ms K Swetha Reddy Ms K Swetha Reddy of VNR Vignana Jyothi Institute of Engineering and Technology

Topic:

Verilog HDL and its Importance

Biography:

Assistant Professor, Dept. of ECE

Teaching Interests: VLSI Design, HDL Verification, Micro controllers and its Applications, Microprocessors, CPLD & FPGA Architectures & Applications.




Agenda

The goal of the lecture was to familiarize the participants with the importance of verilog HDL.  The main idea was to explain that Verilog allows designers to confide in the design by reducing the chances of failure. Further, it accelerates simulation which reduces the time-to-market. With all these benefits, it is impossible for the circuit designers to not use Verilog for hardware description and verification. 


About 45 people attended this webinar and it helped the participants understand the significance of Verilog. It focused mainly on flexible modeling capabilities and Complexity hiding by abstraction is natural of verilog.


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